公开(公告)号：US07429894B2

公开(公告)日：2008-09-30

申请号：US11519668

申请日：2006-09-12

申请人： Woo Jin Chang ,  Jae Kyoung Mun ,  Haecheon Kim ,  Jong Won Lim ,  Hong Gu Ji ,  Ho Kyun Ahn

发明人： Woo Jin Chang ,  Jae Kyoung Mun ,  Haecheon Kim ,  Jong Won Lim ,  Hong Gu Ji ,  Ho Kyun Ahn

IPC分类号： H03F3/68

CPC分类号： H03F3/602 ,  H03F3/211 ,  H03F2200/366 ,  H03F2200/447 ,  H03F2200/543 ,  H03F2203/21178

摘要： Provided is a power device having a connection structure compensating for a reactance component, in which transistors are arranged and connected to minimize deterioration of transistor properties caused by heat by compensating for a reactance component causing a phase difference due to transmission lines used for connecting a plurality of transistors in parallel such that the power device to be used for a high-frequency power amplifier outputs high power, and transmitting heat generated by high output power to a heat sink to be dissipated.

摘要翻译： 提供了具有补偿电抗分量的连接结构的功率器件，其中配置并连接晶体管，以通过补偿导致由于用于连接多个元件的传输线引起的相位差的电抗分量来最小化由热引起的晶体管性质的劣化 的晶体管并联，使得用于高频功率放大器的功率器件输出高功率，并将由高输出功率产生的热量传输到散热器。

公开(公告)号：US07387955B2

公开(公告)日：2008-06-17

申请号：US11454721

申请日：2006-06-16

申请人： Ho Kyun Ahn ,  Jong Won Lim ,  Jae Kyoung Mun ,  Hong Gu Ji ,  Woo Jin Chang ,  Hea Cheon Kim

发明人： Ho Kyun Ahn ,  Jong Won Lim ,  Jae Kyoung Mun ,  Hong Gu Ji ,  Woo Jin Chang ,  Hea Cheon Kim

IPC分类号： H01L21/44

CPC分类号： H01L29/812 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/66856 ,  H01L29/778

摘要： A field effect transistor having a T- or Γ-shaped fine gate electrode of which a head portion is wider than a foot portion, and a method for manufacturing the field effect transistor, are provided. A void is formed between the head portion of the gate electrode and a semiconductor substrate using an insulating layer having a multi-layer structure with different etch rates. Since parasitic capacitance between the gate electrode and the semiconductor substrate is reduced by the void, the head portion of the gate electrode can be made large so that gate resistance can be reduced. In addition, since the height of the gate electrode can be adjusted by adjusting the thickness of the insulating layer, device performance as well as process uniformity and repeatability can be improved.

摘要翻译： 提供具有头部比脚部宽的T形或γ形的精细栅电极的场效应晶体管，以及制造场效应晶体管的方法。 使用具有不同蚀刻速率的多层结构的绝缘层，在栅电极的头部和半导体衬底之间形成空隙。 由于栅电极和半导体衬底之间的寄生电容由于空隙而减小，所以能够使栅电极的头部大，能够降低栅极电阻。 此外，由于可以通过调节绝缘层的厚度来调节栅电极的高度，因此可以提高器件性能以及工艺的均匀性和重复性。

公开(公告)号：US07183149B2

公开(公告)日：2007-02-27

申请号：US11180726

申请日：2005-07-14

申请人： Ho Kyun Ahn ,  Jong Won Lim ,  Hong Gu Ji ,  Woo Jin Chang ,  Jae Kyoung Mun ,  Hae Cheon Kim

发明人： Ho Kyun Ahn ,  Jong Won Lim ,  Hong Gu Ji ,  Woo Jin Chang ,  Jae Kyoung Mun ,  Hae Cheon Kim

IPC分类号： H01L21/338

CPC分类号： H01L29/66856 ,  H01L29/66462

摘要： Provided is a method of manufacturing a field effect transistor (FET). The method includes steps of: forming an ohmic metal layer on a substrate in source and drain regions; sequentially forming an insulating layer and a multilayered resist layer on the entire surface of the resultant structure and simultaneously forming resist patterns having respectively different shapes in both a first region excluding the ohmic metal layer and a second region excluding the ohmic metal layer, wherein a lowermost resist pattern is exposed in the first region, and the insulating layer is exposed in the second region; exposing the substrate and the insulating layer by simultaneously etching the exposed insulating layer and the exposed lowermost resist pattern using the resist patterns as etch masks, respectively; performing a recess process on the exposed substrate and etching the exposed insulating layer to expose the substrate; and forming gate recess regions having different etching depths from each other over the substrate, depositing a predetermined gate metal, and removing the resist patterns. In this method, transistors having different threshold voltages can be manufactured without additional mask patterns using the least number of processes, with the results that the cost of production can be reduced and the stability and productivity of semiconductor devices can be improved.

摘要翻译： 提供了制造场效应晶体管（FET）的方法。 该方法包括以下步骤：在源极和漏极区域的衬底上形成欧姆金属层; 在所得结构的整个表面上顺序地形成绝缘层和多层抗蚀剂层，并且同时形成除了欧姆金属层以外的第一区域和不包括欧姆金属层的第二区域中具有不同形状的抗蚀剂图案，其中最下面 抗蚀剂图案在第一区域中暴露，并且绝缘层在第二区域中暴露; 通过分别使用抗蚀剂图案作为蚀刻掩模，同时蚀刻暴露的绝缘层和暴露的最下面的抗蚀剂图案来暴露衬底和绝缘层; 对曝光的衬底进行凹陷处理并蚀刻暴露的绝缘层以露出衬底; 以及在衬底上形成具有彼此不同蚀刻深度的栅极凹陷区域，沉积预定的栅极金属和去除抗蚀剂图案。 在该方法中，可以使用最少数量的工艺来制造具有不同阈值电压的晶体管，而不需要额外的掩模图案，结果可以降低生产成本，并且可以提高半导体器件的稳定性和生产率。

公开(公告)号：US07973368B2

公开(公告)日：2011-07-05

申请号：US12122982

申请日：2008-05-19

申请人： Jong Won Lim ,  Ho Kyun Ahn ,  Hong Gu Ji ,  Woo Jin Chang ,  Jae Kyoung Mun ,  Hae Cheon Kim ,  Hyun Kyu Yu

发明人： Jong Won Lim ,  Ho Kyun Ahn ,  Hong Gu Ji ,  Woo Jin Chang ,  Jae Kyoung Mun ,  Hae Cheon Kim ,  Hyun Kyu Yu

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/778 ,  H01L29/20 ,  H01L29/42316 ,  H01L29/66462

摘要： Provided are a semiconductor device with a T-gate electrode capable of improving stability and a high frequency characteristic of the semiconductor device by reducing source resistance, parasitic capacitance, and gate resistance and a method of fabricating the same. In the semiconductor device, in order to form source and drain electrodes and the T-gate electrode on a substrate, first and second protective layers constructed with silicon oxide layers or silicon nitride layers are formed on sides of a supporting part under a head part of the T-gate electrode, and the second protective layer constructed with a silicon oxide layer or silicon nitride layer is formed on sides of the source and drain electrodes. Accordingly, it is possible to protect an activated region of the semiconductor device and reduce gate-drain parasitic capacitance and gate-source parasitic capacitance.

摘要翻译： 提供一种具有T栅电极的半导体器件及其制造方法，该半导体器件能够通过降低源极电阻，寄生电容和栅极电阻来提高半导体器件的稳定性和高频特性。 在半导体器件中，为了在衬底上形成源电极和漏电极以及T栅电极，在氧化硅层或氮化硅层构成的第一和第二保护层形成在支撑部分的头部 在栅电极和漏电极的侧面上形成T形栅电极和由氧化硅层或氮化硅层构成的第二保护层。 因此，可以保护半导体器件的激活区域并减小栅极 - 漏极寄生电容和栅极 - 源极寄生电容。

公开(公告)号：US07902572B2

公开(公告)日：2011-03-08

申请号：US12122805

申请日：2008-05-19

申请人： Ho Kyun Ahn ,  Jong Won Lim ,  Jae Kyoung Mun ,  Hong Gu Ji ,  Woo Jin Chang ,  Hea Cheon Kim

发明人： Ho Kyun Ahn ,  Jong Won Lim ,  Jae Kyoung Mun ,  Hong Gu Ji ,  Woo Jin Chang ,  Hea Cheon Kim

IPC分类号： H01L31/072

CPC分类号： H01L29/812 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/66856 ,  H01L29/778

摘要： A field effect transistor having a T- or Γ-shaped fine gate electrode of which a head portion is wider than a foot portion, and a method for manufacturing the field effect transistor, are provided. A void is formed between the head portion of the gate electrode and a semiconductor substrate using an insulating layer having a multi-layer structure with different etch rates. Since parasitic capacitance between the gate electrode and the semiconductor substrate is reduced by the void, the head portion of the gate electrode can be made large so that gate resistance can be reduced. In addition, since the height of the gate electrode can be adjusted by adjusting the thickness of the insulating layer, device performance as well as process uniformity and repeatability can be improved.

摘要翻译： 提供了具有头部比脚部宽的T形或/或G字形精细栅电极的场效应晶体管，以及制造场效应晶体管的方法。 使用具有不同蚀刻速率的多层结构的绝缘层，在栅电极的头部和半导体衬底之间形成空隙。 由于栅电极和半导体衬底之间的寄生电容由于空隙而减小，所以能够使栅电极的头部大，能够降低栅极电阻。 此外，由于可以通过调节绝缘层的厚度来调节栅电极的高度，因此可以提高器件性能以及工艺的均匀性和重复性。

公开(公告)号：US07871874B2

公开(公告)日：2011-01-18

申请号：US12396614

申请日：2009-03-03

申请人： Jae Kyoung Mun ,  Jong Won Lim ,  Woo Jin Chang ,  Hong Gu Ji ,  Ho Kyun Ahn ,  Hae Cheon Kim

发明人： Jae Kyoung Mun ,  Jong Won Lim ,  Woo Jin Chang ,  Hong Gu Ji ,  Ho Kyun Ahn ,  Hae Cheon Kim

IPC分类号： H01L21/338

CPC分类号： H01L29/66462 ,  H01L29/7785

摘要： Provided are a transistor of a semiconductor device and method of fabricating the same. The transistor includes: an epitaxy substrate disposed on a semi-insulating substrate and having a buffer layer, a first Si planar doping layer, a first conductive layer, a second Si planar doping layer, and a second conductive layer, which are sequentially stacked, the second Si planar doping layer having a doping concentration different from that of the first Si planar doping layer; a source electrode and a drain electrode diffusing into the first Si planar doping layer to a predetermined depth and disposed on both sides of the second conductive layer to form an ohmic contact; and a gate electrode disposed on the second conductive layer between the source and drain electrodes and being in contact with the second conductive layer. In this structure, both isolation and switching speed of the transistor can be increased. Also, the maximum voltage limit applied to the transistor is increased due to increases in gate turn-on voltage and threshold voltage and a reduction in parallel conduction element. As a result, the power handling capability of the transistor can be improved, thus improving a high-power low-distortion characteristic and an isolation characteristic.

摘要翻译： 提供半导体器件的晶体管及其制造方法。 晶体管包括：设置在半绝缘衬底上并具有缓冲层的外延衬底，第一Si平面掺杂层，第一导电层，第二Si平面掺杂层和第二导电层， 所述第二Si平面掺杂层具有与所述第一Si平面掺杂层的掺杂浓度不同的掺杂浓度; 源极电极和漏电极，其扩散到所述第一Si平面掺杂层中至预定深度并且设置在所述第二导电层的两侧以形成欧姆接触; 以及设置在所述源极和漏极之间的所述第二导电层上并与所述第二导电层接触的栅电极。 在这种结构中，可以提高晶体管的隔离和开关速度。 此外，施加到晶体管的最大电压限制由于栅极导通电压和阈值电压的增加以及并联导通元件的减小而增加。 结果，可以提高晶体管的功率处理能力，从而提高高功率低失真特性和隔离特性。

公开(公告)号：US07518166B2

公开(公告)日：2009-04-14

申请号：US11179971

申请日：2005-07-12

申请人： Jae Kyoung Mun ,  Jong Won Lim ,  Woo Jin Chang ,  Hong Gu Ji ,  Ho Kyun Ahn ,  Hae Cheon Kim

发明人： Jae Kyoung Mun ,  Jong Won Lim ,  Woo Jin Chang ,  Hong Gu Ji ,  Ho Kyun Ahn ,  Hae Cheon Kim

IPC分类号： H01L29/74

CPC分类号： H01L29/66462 ,  H01L29/7785

摘要： Provided are a transistor of a semiconductor device and method of fabricating the same. The transistor includes: an epitaxy substrate disposed on a semi-insulating substrate and having a buffer layer, a first Si planar doping layer, a first conductive layer, a second Si planar doping layer, and a second conductive layer, which are sequentially stacked, the second Si planar doping layer having a doping concentration different from that of the first Si planar doping layer; a source electrode and a drain electrode diffusing into the first Si planar doping layer to a predetermined depth and disposed on both sides of the second conductive layer to form an ohmic contact; and a gate electrode disposed on the second conductive layer between the source and drain electrodes and being in contact with the second conductive layer. In this structure, both isolation and switching speed of the transistor can be increased. Also, the maximum voltage limit applied to the transistor is increased due to increases in gate turn-on voltage and threshold voltage and a reduction in parallel conduction element. As a result, the power handling capability of the transistor can be improved, thus improving a high-power low-distortion characteristic and an isolation characteristic.

摘要翻译： 提供半导体器件的晶体管及其制造方法。 晶体管包括：设置在半绝缘衬底上并具有缓冲层的外延衬底，第一Si平面掺杂层，第一导电层，第二Si平面掺杂层和第二导电层， 所述第二Si平面掺杂层具有与所述第一Si平面掺杂层的掺杂浓度不同的掺杂浓度; 源极电极和漏电极，其扩散到所述第一Si平面掺杂层中至预定深度并且设置在所述第二导电层的两侧以形成欧姆接触; 以及设置在所述源极和漏极之间的所述第二导电层上并与所述第二导电层接触的栅电极。 在这种结构中，可以提高晶体管的隔离和开关速度。 此外，施加到晶体管的最大电压限制由于栅极导通电压和阈值电压的增加以及并联导通元件的减小而增加。 结果，可以提高晶体管的功率处理能力，从而提高高功率低失真特性和隔离特性。

公开(公告)号：US07419862B2

公开(公告)日：2008-09-02

申请号：US11446750

申请日：2006-06-05

申请人： Jong Won Lim ,  Ho Kyun Ahn ,  Hong Gu Ji ,  Woo Jin Chang ,  Jae Kyoung Mun ,  Hea Cheon Kim

发明人： Jong Won Lim ,  Ho Kyun Ahn ,  Hong Gu Ji ,  Woo Jin Chang ,  Jae Kyoung Mun ,  Hea Cheon Kim

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/7784 ,  H01L29/1029 ,  H01L29/66462

摘要： Provided is a method of fabricating a pseudomorphic high electron mobility transistor (PHEMT). The method includes the steps of: preparing a substrate including a channel layer and a capping layer that is the uppermost layer; forming a source and a drain on the capping layer; forming a first protective layer on the entire surface of the resultant structure and then patterning the first protective layer to expose a portion of the capping layer in a channel region; removing the exposed portion of the capping layer to form a first recess structure; forming a second protective layer on the entire surface of the resultant structure and then patterning the second protective layer to expose a portion of the substrate in the first recess structure so that a second recess structure is formed; forming a multilayered photoresist layer on the entire surface of the resultant structure and then patterning the multilayered photoresist layer to expose a portion of the substrate through the second recess structure and form a gate-shaped opening; and depositing a metal layer to fill the gate-shaped opening and then removing the multilayered photoresist layer to form a gate connected to the substrate through the second recess structure.

摘要翻译： 提供了制造假象高电子迁移率晶体管（PHEMT）的方法。 该方法包括以下步骤：制备包括沟道层和作为最上层的覆盖层的衬底; 在封盖层上形成源极和漏极; 在所得结构的整个表面上形成第一保护层，然后图案化第一保护层以暴露沟道区中的覆盖层的一部分; 去除所述覆盖层的暴露部分以形成第一凹陷结构; 在所得结构的整个表面上形成第二保护层，然后构图第二保护层，以暴露第一凹陷结构中的基底的一部分，从而形成第二凹陷结构; 在所得结构的整个表面上形成多层光致抗蚀剂层，然后构图多层光致抗蚀剂层，以通过第二凹陷结构暴露出基板的一部分并形成栅极形开口; 以及沉积金属层以填充所述栅极开口，然后移除所述多层光致抗蚀剂层，以形成通过所述第二凹陷结构连接到所述衬底的栅极。

公开(公告)号：US20070134862A1

公开(公告)日：2007-06-14

申请号：US11446750

申请日：2006-06-05

申请人： Jong Won Lim ,  Ho Kyun Ahn ,  Hong Gu Ji ,  Woo Jin Chang ,  Jae Kyoung Mun ,  Hea Cheon Kim

发明人： Jong Won Lim ,  Ho Kyun Ahn ,  Hong Gu Ji ,  Woo Jin Chang ,  Jae Kyoung Mun ,  Hea Cheon Kim

IPC分类号： H01L21/8234

CPC分类号： H01L29/7784 ,  H01L29/1029 ,  H01L29/66462

摘要： Provided is a method of fabricating a pseudomorphic high electron mobility transistor (PHEMT). The method includes the steps of: preparing a substrate including a channel layer and a capping layer that is the uppermost layer; forming a source and a drain on the capping layer; forming a first protective layer on the entire surface of the resultant structure and then patterning the first protective layer to expose a portion of the capping layer in a channel region; removing the exposed portion of the capping layer to form a first recess structure; forming a second protective layer on the entire surface of the resultant structure and then patterning the second protective layer to expose a portion of the substrate in the first recess structure so that a second recess structure is formed; forming a multilayered photoresist layer on the entire surface of the resultant structure and then patterning the multilayered photoresist layer to expose a portion of the substrate through the second recess structure and form a gate-shaped opening; and depositing a metal layer to fill the gate-shaped opening and then removing the multilayered photoresist layer to form a gate connected to the substrate through the second recess structure.

摘要翻译： 提供了制造假象高电子迁移率晶体管（PHEMT）的方法。 该方法包括以下步骤：制备包括沟道层和作为最上层的覆盖层的衬底; 在封盖层上形成源极和漏极; 在所得结构的整个表面上形成第一保护层，然后图案化第一保护层以暴露沟道区中的覆盖层的一部分; 去除所述覆盖层的暴露部分以形成第一凹陷结构; 在所得结构的整个表面上形成第二保护层，然后构图第二保护层，以暴露第一凹陷结构中的基底的一部分，从而形成第二凹陷结构; 在所得结构的整个表面上形成多层光致抗蚀剂层，然后构图多层光致抗蚀剂层，以通过第二凹陷结构暴露出基板的一部分并形成栅极形开口; 以及沉积金属层以填充所述栅极开口，然后移除所述多层光致抗蚀剂层，以形成通过所述第二凹陷结构连接到所述衬底的栅极。

公开(公告)号：US20080124852A1

公开(公告)日：2008-05-29

申请号：US11605508

申请日：2006-11-28

申请人： Ho Kyun Ahn ,  Jong Won Lim ,  Jae Kyoung Mun ,  Woo Jin Chang ,  Hong Gu Ji ,  Hae Cheon Kim

发明人： Ho Kyun Ahn ,  Jong Won Lim ,  Jae Kyoung Mun ,  Woo Jin Chang ,  Hong Gu Ji ,  Hae Cheon Kim

IPC分类号： H01L21/338

CPC分类号： H01L29/4232 ,  H01L21/28587 ,  H01L21/28593

摘要： A method of forming a fine T- or gamma-shaped gate electrode is provided, which is performed by a lithography process using a multi-layered photoresist layer having various sensitivities, deposition of an insulating layer, and an etching process. The method includes: a first step of depositing a first insulating layer on a semiconductor substrate; a second step of coating at least two photoresist layers with different sensitivities from each other on the first insulating layer, and patterning the photoresist layers to have openings which are different in size; a third step of etching the first insulating layer using the photoresist layers as etch masks to form a step hole in which a part contacting the substrate is narrower than an upper part thereof, and removing the photoresist layers; a fourth step of forming a photoresist layer on the first insulating layer, and forming an opening in the photoresist layer to have a T- or gamma-shaped gate head pattern; a fifth step of performing a gate recess process with respect to the gate pattern; and a sixth step of depositing a gate metal on the gate pattern, and removing the photoresist layers.

摘要翻译： 提供了一种通过使用具有各种灵敏度的多层光致抗蚀剂层，沉积绝缘层和蚀刻工艺的光刻工艺来形成精细的T形或γ形栅电极的方法。 该方法包括：在半导体衬底上沉积第一绝缘层的第一步骤; 在所述第一绝缘层上涂覆彼此具有不同灵敏度的至少两个光致抗蚀剂层的第二步骤，以及使所述光致抗蚀剂层图案化以具有尺寸不同的开口; 使用光致抗蚀剂层作为蚀刻掩模来蚀刻第一绝缘层以形成步骤孔的第三步骤，其中与衬底接触的部分比其上部更窄，并且去除光致抗蚀剂层; 在所述第一绝缘层上形成光致抗蚀剂层，以及在所述光致抗蚀剂层中形成具有T形或γ形门头图案的开口的第四步骤; 执行相对于栅极图案的栅极凹槽工艺的第五步骤; 以及在栅极图案上沉积栅极金属和去除光致抗蚀剂层的第六步骤。