公开(公告)号：US20060291077A1

公开(公告)日：2006-12-28

申请号：US11451580

申请日：2006-06-13

申请人： Woo-Seok Shim ,  Jung-Hyeon Lee ,  Young-Koog Han ,  Kwang-Sub Yoon ,  Si-Hyeung Lee

发明人： Woo-Seok Shim ,  Jung-Hyeon Lee ,  Young-Koog Han ,  Kwang-Sub Yoon ,  Si-Hyeung Lee

IPC分类号： G02B7/02

CPC分类号： G02B7/00 ,  G03F7/701 ,  G03F7/70825

摘要： In an optical member holder and a projection exposure apparatus having the same, a light beam radiated from a light source may be formed into light having a desired shape by selecting one of a plurality of optical elements. An optical element holder may include a support member to support the plurality of optical elements, a first driving section to move or rotate the support member to select one of the optical elements, and a second driving section to rotate the selected optical element to adjust an arrangement direction thereof. The light formed by the selected optical element may be directed through a reticle.

摘要翻译： 在具有该光学构件保持器和投影曝光设备的光学构件保持器和投影曝光设备中，从光源辐射的光束可以通过选择多个光学元件之一形成具有所需形状的光。 光学元件保持器可以包括用于支撑多个光学元件的支撑构件，用于移动或旋转支撑构件以选择一个光学元件的第一驱动部分和第二驱动部分，以旋转所选择的光学元件以调整 排列方向。 由所选择的光学元件形成的光可以被引导通过掩模版。

公开(公告)号：US07457058B2

公开(公告)日：2008-11-25

申请号：US11451580

申请日：2006-06-13

申请人： Woo-Seok Shim ,  Jung-Hyeon Lee ,  Young-Koog Han ,  Kwang-Sub Yoon ,  Si-Hyeung Lee

发明人： Woo-Seok Shim ,  Jung-Hyeon Lee ,  Young-Koog Han ,  Kwang-Sub Yoon ,  Si-Hyeung Lee

IPC分类号： G02B26/02

CPC分类号： G02B7/00 ,  G03F7/701 ,  G03F7/70825

摘要： In an optical member holder and a projection exposure apparatus having the same, a light beam radiated from a light source may be formed into light having a desired shape by selecting one of a plurality of optical elements. An optical element holder may include a support member to support the plurality of optical elements, a first driving section to move or rotate the support member to select one of the optical elements, and a second driving section to rotate the selected optical element to adjust an arrangement direction thereof. The light formed by the selected optical element may be directed through a reticle.

摘要翻译： 在具有该光学构件保持器和投影曝光设备的光学构件保持器和投影曝光设备中，从光源辐射的光束可以通过选择多个光学元件之一形成具有所需形状的光。 光学元件保持器可以包括用于支撑多个光学元件的支撑构件，用于移动或旋转支撑构件以选择一个光学元件的第一驱动部分和第二驱动部分，以旋转所选择的光学元件以调整 排列方向。 由所选择的光学元件形成的光可以被引导通过掩模版。

公开(公告)号：US20060284259A1

公开(公告)日：2006-12-21

申请号：US11449689

申请日：2006-06-09

申请人： Jung-Hyeon Lee ,  Si-Hyeung Lee ,  Kwang-Sub Yoon ,  Bong-Cheol Kim

发明人： Jung-Hyeon Lee ,  Si-Hyeung Lee ,  Kwang-Sub Yoon ,  Bong-Cheol Kim

IPC分类号： H01L29/76

CPC分类号： H01L27/0207 ,  H01L27/10817 ,  H01L27/10885

摘要： In a semiconductor device having asymmetric bit lines and a method of manufacturing the same, a plurality of active regions are electrically isolated from one another by an isolation layer. Each active region extends in a first direction and has a central portion between end portions. The device includes a plurality of transistors, each including first impurity doped regions formed at the central portions and second impurity doped regions formed at both end portions to extend in a second direction different from the first direction. A plurality of asymmetric bit lines are electrically connected to the first impurity doped regions, each extending in a third direction substantially perpendicular to the second direction. Each asymmetric bit line has a first side surface extending in a straight line along the third direction, and a second side surface including a plurality of protrusions.

摘要翻译： 在具有不对称位线的半导体器件及其制造方法中，多个有源区域通过隔离层彼此电隔离。 每个有源区域在第一方向上延伸并且在端部之间具有中心部分。 该器件包括多个晶体管，每个晶体管包括形成在中心部分的第一杂质掺杂区域和形成在两个端部处的第二杂质掺杂区域，以沿与第一方向不同的第二方向延伸。 多个非对称位线电连接到第一杂质掺杂区域，每个第一杂质掺杂区域在基本上垂直于第二方向的第三方向上延伸。 每个不对称位线具有沿着第三方向在直线上延伸的第一侧表面和包括多个突起的第二侧表面。

公开(公告)号：US20110156159A1

公开(公告)日：2011-06-30

申请号：US13064138

申请日：2011-03-08

申请人： Man-Hyoung Ryoo ,  Gi-Sung Yeo ,  Si-Hyeung Lee ,  Gyu-Chul Kim ,  Sung-Gon Jung ,  Chang-Min Park ,  Hoo-Sung Cho

发明人： Man-Hyoung Ryoo ,  Gi-Sung Yeo ,  Si-Hyeung Lee ,  Gyu-Chul Kim ,  Sung-Gon Jung ,  Chang-Min Park ,  Hoo-Sung Cho

IPC分类号： H01L27/092 ,  H01L21/28

CPC分类号： H01L27/088 ,  G11C11/412 ,  H01L27/0203 ,  H01L27/1104 ,  Y10S257/903

摘要： According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.

摘要翻译： 根据本发明的一些实施例，提供掺杂有P型杂质的衬底。 在衬底中掺杂N型杂质以将衬底分成P型杂质区和N型杂质区。 在P型和N型杂质区中形成具有第一间距的有源图案。 具有第二间距的栅极图案在与有源图案基本垂直的方向上形成在有源图案上。 描述和要求保护其他实施例。

公开(公告)号：US20100190303A1

公开(公告)日：2010-07-29

申请号：US12654798

申请日：2010-01-04

申请人： Man-Hyoung Ryoo ,  Gi-Sung Yeo ,  Si-Hyeung Lee ,  Gyu-Chul Kim ,  Sung-Gon Jung ,  Chang-Min Park ,  Hoo-Sung Cho

发明人： Man-Hyoung Ryoo ,  Gi-Sung Yeo ,  Si-Hyeung Lee ,  Gyu-Chul Kim ,  Sung-Gon Jung ,  Chang-Min Park ,  Hoo-Sung Cho

IPC分类号： H01L21/8239

CPC分类号： H01L27/088 ,  G11C11/412 ,  H01L27/0203 ,  H01L27/1104 ,  Y10S257/903

摘要： According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.

摘要翻译： 根据本发明的一些实施例，提供掺杂有P型杂质的衬底。 在衬底中掺杂N型杂质以将衬底分成P型杂质区和N型杂质区。 在P型和N型杂质区中形成具有第一间距的有源图案。 具有第二间距的栅极图案在与有源图案基本垂直的方向上形成在有源图案上。 描述和要求保护其他实施例。

公开(公告)号：US08193047B2

公开(公告)日：2012-06-05

申请号：US12654798

申请日：2010-01-04

申请人： Man-Hyoung Ryoo ,  Gi-Sung Yeo ,  Si-Hyeung Lee ,  Gyu-Chul Kim ,  Sung-Gon Jung ,  Chang-Min Park ,  Hoo-Sung Cho

发明人： Man-Hyoung Ryoo ,  Gi-Sung Yeo ,  Si-Hyeung Lee ,  Gyu-Chul Kim ,  Sung-Gon Jung ,  Chang-Min Park ,  Hoo-Sung Cho

IPC分类号： H01L21/8239

CPC分类号： H01L27/088 ,  G11C11/412 ,  H01L27/0203 ,  H01L27/1104 ,  Y10S257/903

摘要： According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.

摘要翻译： 根据本发明的一些实施例，提供掺杂有P型杂质的衬底。 在衬底中掺杂N型杂质以将衬底分成P型杂质区和N型杂质区。 在P型和N型杂质区中形成具有第一间距的有源图案。 具有第二间距的栅极图案在与有源图案基本垂直的方向上形成在有源图案上。 描述和要求保护其他实施例。

公开(公告)号：US08080886B2

公开(公告)日：2011-12-20

申请号：US12111651

申请日：2008-04-29

申请人： Chang-Jin Kang ,  Myeong-Cheol Kim ,  Man-Hyoung Ryoo ,  Si-Hyeung Lee ,  Doo-Youl Lee

发明人： Chang-Jin Kang ,  Myeong-Cheol Kim ,  Man-Hyoung Ryoo ,  Si-Hyeung Lee ,  Doo-Youl Lee

IPC分类号： H01L23/544

CPC分类号： H01L23/544 ,  G03F7/70633 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit semiconductor device including a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern. An overlay key region is formed in a second portion of the silicon substrate and includes a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern and formed by correcting overlay and alignment errors using the second insulating pattern. An alignment key region is formed in a third portion of the silicon substrate and includes a third trench formed in the silicon substrate and used as an alignment key, a second buried insulating layer formed in the third trench, and a third conductive pattern formed over the second buried insulating layer and the third trench.

摘要翻译： 一种集成电路半导体器件，包括形成在硅衬底的第一部分中的单元区域，所述单元区域包括形成在所述硅衬底中的第一沟槽，填充在所述第一沟槽中的第一掩埋绝缘层，形成在所述第一沟槽上的第一绝缘图案 硅衬底和形成在第一绝缘图案上的第一导电图案。 覆盖键区域形成在硅衬底的第二部分中，并且包括在硅衬底中形成的第二沟槽，形成在硅衬底上并用作覆盖键的第二绝缘图案，以及形成在第二衬底上的第二导电图案 绝缘图案，并且通过使用第二绝缘图案校正覆盖和对准误差而形成。 对准键区域形成在硅衬底的第三部分中，并且包括形成在硅衬底中并用作对准键的第三沟槽，形成在第三沟槽中的第二掩埋绝缘层和形成在第三沟槽上的第三导电图案 第二掩埋绝缘层和第三沟槽。

公开(公告)号：US07381508B2

公开(公告)日：2008-06-03

申请号：US10867468

申请日：2004-06-14

申请人： Chang-Jin Kang ,  Myeong-Cheol Kim ,  Man-Hyoung Ryoo ,  Si-Hyeung Lee ,  Doo-Youl Lee

发明人： Chang-Jin Kang ,  Myeong-Cheol Kim ,  Man-Hyoung Ryoo ,  Si-Hyeung Lee ,  Doo-Youl Lee

IPC分类号： G03F9/00 ,  G03F7/20

CPC分类号： H01L23/544 ,  G03F7/70633 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit semiconductor device including a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern. An overlay key region is formed in a second portion of the silicon substrate and includes a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern and formed by correcting overlay and alignment errors using the second insulating pattern. An alignment key region is formed in a third portion of the silicon substrate and includes a third trench formed in the silicon substrate and used as an alignment key, a second buried insulating layer formed in the third trench, and a third conductive pattern formed over the second buried insulating layer and the third trench.

摘要翻译： 一种集成电路半导体器件，包括形成在硅衬底的第一部分中的单元区域，所述单元区域包括形成在所述硅衬底中的第一沟槽，填充在所述第一沟槽中的第一掩埋绝缘层，形成在所述第一沟槽上的第一绝缘图案 硅衬底和形成在第一绝缘图案上的第一导电图案。 覆盖键区域形成在硅衬底的第二部分中，并且包括在硅衬底中形成的第二沟槽，形成在硅衬底上并用作覆盖键的第二绝缘图案，以及形成在第二衬底上的第二导电图案 绝缘图案，并且通过使用第二绝缘图案校正覆盖和对准误差而形成。 对准键区域形成在硅衬底的第三部分中，并且包括形成在硅衬底中并用作对准键的第三沟槽，形成在第三沟槽中的第二掩埋绝缘层和形成在第三沟槽上的第三导电图案 第二掩埋绝缘层和第三沟槽。

公开(公告)号：US07221031B2

公开(公告)日：2007-05-22

申请号：US10892588

申请日：2004-07-15

申请人： Man-Hyoung Ryoo ,  Gi-Sung Yeo ,  Si-Hyeung Lee ,  Gyu-Chul Kim ,  Sung-Gon Jung ,  Chang-Min Park ,  Hoo-Sung Cho

发明人： Man-Hyoung Ryoo ,  Gi-Sung Yeo ,  Si-Hyeung Lee ,  Gyu-Chul Kim ,  Sung-Gon Jung ,  Chang-Min Park ,  Hoo-Sung Cho

IPC分类号： H01L27/11

CPC分类号： H01L27/088 ,  G11C11/412 ,  H01L27/0203 ,  H01L27/1104 ,  Y10S257/903

摘要： According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.

摘要翻译： 根据本发明的一些实施例，提供掺杂有P型杂质的衬底。 在衬底中掺杂N型杂质以将衬底分成P型杂质区和N型杂质区。 在P型和N型杂质区中形成具有第一间距的有源图案。 具有第二间距的栅极图案在与有源图案基本垂直的方向上形成在有源图案上。 描述和要求保护其他实施例。

公开(公告)号：US20050031995A1

公开(公告)日：2005-02-10

申请号：US10867468

申请日：2004-06-14

申请人： Chang-Jin Kang ,  Myeong-Cheol Kim ,  Man-Hyoung Ryoo ,  Si-Hyeung Lee ,  Doo-Youl Lee

发明人： Chang-Jin Kang ,  Myeong-Cheol Kim ,  Man-Hyoung Ryoo ,  Si-Hyeung Lee ,  Doo-Youl Lee

IPC分类号： G03F9/00 ,  G03F7/00 ,  G03F7/20 ,  H01L21/027 ,  H01L23/544

CPC分类号： H01L23/544 ,  G03F7/70633 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit semiconductor device including a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern. An overlay key region is formed in a second portion of the silicon substrate and includes a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern and formed by correcting overlay and alignment errors using the second insulating pattern. An alignment key region is formed in a third portion of the silicon substrate and includes a third trench formed in the silicon substrate and used as an alignment key, a second buried insulating layer formed in the third trench, and a third conductive pattern formed over the second buried insulating layer and the third trench.

摘要翻译： 一种集成电路半导体器件，包括形成在硅衬底的第一部分中的单元区域，所述单元区域包括形成在所述硅衬底中的第一沟槽，填充在所述第一沟槽中的第一掩埋绝缘层，形成在所述第一沟槽上的第一绝缘图案 硅衬底和形成在第一绝缘图案上的第一导电图案。 覆盖键区域形成在硅衬底的第二部分中，并且包括在硅衬底中形成的第二沟槽，形成在硅衬底上并用作覆盖键的第二绝缘图案，以及形成在第二衬底上的第二导电图案 绝缘图案，并且通过使用第二绝缘图案校正覆盖和对准误差而形成。 对准键区域形成在硅衬底的第三部分中，并且包括形成在硅衬底中并用作对准键的第三沟槽，形成在第三沟槽中的第二掩埋绝缘层和形成在第三沟槽上的第三导电图案 第二掩埋绝缘层和第三沟槽。