公开(公告)号：US08193047B2

公开(公告)日：2012-06-05

申请号：US12654798

申请日：2010-01-04

Applicant: Man-Hyoung Ryoo ,  Gi-Sung Yeo ,  Si-Hyeung Lee ,  Gyu-Chul Kim ,  Sung-Gon Jung ,  Chang-Min Park ,  Hoo-Sung Cho

Inventor： Man-Hyoung Ryoo ,  Gi-Sung Yeo ,  Si-Hyeung Lee ,  Gyu-Chul Kim ,  Sung-Gon Jung ,  Chang-Min Park ,  Hoo-Sung Cho

IPC: H01L21/8239

CPC classification number: H01L27/088 ,  G11C11/412 ,  H01L27/0203 ,  H01L27/1104 ,  Y10S257/903

Abstract: According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.

Abstract translation: 根据本发明的一些实施例，提供掺杂有P型杂质的衬底。 在衬底中掺杂N型杂质以将衬底分成P型杂质区和N型杂质区。 在P型和N型杂质区中形成具有第一间距的有源图案。 具有第二间距的栅极图案在与有源图案基本垂直的方向上形成在有源图案上。 描述和要求保护其他实施例。

公开(公告)号：US20070190812A1

公开(公告)日：2007-08-16

申请号：US11737675

申请日：2007-04-19

Applicant: Man-Hyoung RYOO ,  Gi-Sung YEO ,  Si-Hyeung LEE ,  Gyu-Chul KIM ,  Sung-Gon JUNG ,  Chang-Min PARK ,  Hoo-Sung CHO

Inventor： Man-Hyoung RYOO ,  Gi-Sung YEO ,  Si-Hyeung LEE ,  Gyu-Chul KIM ,  Sung-Gon JUNG ,  Chang-Min PARK ,  Hoo-Sung CHO

IPC: H01L21/027

CPC classification number: H01L27/088 ,  G11C11/412 ,  H01L27/0203 ,  H01L27/1104 ,  Y10S257/903

Abstract: According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.

Abstract translation: 根据本发明的一些实施例，提供掺杂有P型杂质的衬底。 在衬底中掺杂N型杂质以将衬底分成P型杂质区和N型杂质区。 在P型和N型杂质区中形成具有第一间距的有源图案。 具有第二间距的栅极图案在与有源图案基本垂直的方向上形成在有源图案上。 描述和要求保护其他实施例。

公开(公告)号：US07221031B2

公开(公告)日：2007-05-22

申请号：US10892588

申请日：2004-07-15

Applicant: Man-Hyoung Ryoo ,  Gi-Sung Yeo ,  Si-Hyeung Lee ,  Gyu-Chul Kim ,  Sung-Gon Jung ,  Chang-Min Park ,  Hoo-Sung Cho

Inventor： Man-Hyoung Ryoo ,  Gi-Sung Yeo ,  Si-Hyeung Lee ,  Gyu-Chul Kim ,  Sung-Gon Jung ,  Chang-Min Park ,  Hoo-Sung Cho

IPC: H01L27/11

CPC classification number: H01L27/088 ,  G11C11/412 ,  H01L27/0203 ,  H01L27/1104 ,  Y10S257/903

Abstract: According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.

Abstract translation: 根据本发明的一些实施例，提供掺杂有P型杂质的衬底。 在衬底中掺杂N型杂质以将衬底分成P型杂质区和N型杂质区。 在P型和N型杂质区中形成具有第一间距的有源图案。 具有第二间距的栅极图案在与有源图案基本垂直的方向上形成在有源图案上。 描述和要求保护其他实施例。

公开(公告)号：US20060189088A1

公开(公告)日：2006-08-24

申请号：US11381509

申请日：2006-05-03

Applicant: Kang-Sik CHO ,  Gyu-Chul KIM ,  Hoo-Sung CHO

Inventor： Kang-Sik CHO ,  Gyu-Chul KIM ,  Hoo-Sung CHO

IPC: H01L21/331 ,  H01L21/44

CPC classification number: H01L29/66659 ,  H01L21/28518 ,  H01L21/743 ,  H01L21/823814 ,  H01L29/665

Abstract: A semiconductor device includes an insulated gate electrode pattern formed on a well region. The semiconductor device further includes a sidewall spacer formed on sidewalls of the gate electrode pattern. A source region and a drain region are formed adjacent opposite sides of the gate pattern. In accordance with one embodiment of the present invention, one of the source or drain regions includes a first-concentration impurity region formed under the sidewall spacer. The semiconductor device further includes a silicide layer formed within the well region wherein at least a part of the silicide layer contacts a portion of the well region to bias the well region. A method of manufacturing the semiconductor device is also provided.

Abstract translation: 半导体器件包括形成在阱区上的绝缘栅电极图案。 半导体器件还包括形成在栅电极图案的侧壁上的侧壁间隔物。 源极区域和漏极区域形成在栅极图案的相对侧附近。 根据本发明的一个实施例，源区或漏区中的一个包括形成在侧壁间隔物下方的第一浓度杂质区。 半导体器件还包括形成在阱区内的硅化物层，其中硅化物层的至少一部分接触阱区的一部分以偏置阱区。 还提供了制造半导体器件的方法。

公开(公告)号：US06355515B1

公开(公告)日：2002-03-12

申请号：US09359243

申请日：1999-07-22

Applicant: Jae-hwan Moon ,  Gyu-chul Kim

Inventor： Jae-hwan Moon ,  Gyu-chul Kim

IPC: H01L218244

CPC classification number: H01L21/823475 ,  H01L21/76804 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/823425 ,  H01L27/11

Abstract: A wiring structure of a semiconductor device and a method for manufacturing the same are provided. The wiring structure according to the present invention includes a body formed of a conductive material in a first insulating film on a semiconductor substrate and a protrusion formed of a conductive material in a second insulating film formed on the first insulating film, connected to the upper surface of the body, formed to have a width less than that of the body, and having a planarized upper surface.

Abstract translation: 提供半导体器件的布线结构及其制造方法。 根据本发明的布线结构包括由半导体衬底上的第一绝缘膜中的导电材料形成的本体和在形成在第一绝缘膜上的第二绝缘膜中的由导电材料形成的突起，其连接到上表面 的身体，形成为具有小于身体的宽度的宽度，并且具有平坦化的上表面。

公开(公告)号：US5323379A

公开(公告)日：1994-06-21

申请号：US915505

申请日：1992-07-20

Applicant: Gyu-Chul Kim

Inventor： Gyu-Chul Kim

IPC: G11B17/028 ,  G11B25/04

CPC classification number: G11B17/0282

Abstract: A disk drive mechanism includes a disk clamping apparatus which has an improved structure and which is easily fabricated, thereby to reduce costs. The disk clamping apparatus includes a clamp having a plurality of clamp jaws movable horizontally, such that the apparatus is compact. The clamp also includes first and second grooves formed according to central hole sizes of the disks to be accommodated on the turntable so that the clamp can be used for both a compact disk and a laser disk.

Abstract translation: 磁盘驱动机构包括具有改进的结构并且易于制造的盘夹持装置，从而降低成本。 盘夹紧装置包括具有可水平移动的多个夹钳的夹具，使得该装置紧凑。 夹具还包括根据要容纳在转台上的盘的中心孔尺寸形成的第一和第二槽，使得夹具可用于光盘和激光盘。

公开(公告)号：US20070122970A1

公开(公告)日：2007-05-31

申请号：US11626495

申请日：2007-01-24

Applicant: Gyu-chul Kim ,  Sung-bong Kim

Inventor： Gyu-chul Kim ,  Sung-bong Kim

IPC: H01L21/8242

CPC classification number: H01L29/4983 ,  H01L21/28273 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/11 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7835 ,  Y10S257/90

Abstract: A memory device, such as a DRAM, SRAM or non-volatile memory device, includes a substrate, a gate electrode disposed on the substrate, and source and drain regions in the substrate adjacent respective first and second sidewalls of the gate electrode. First and second sidewall spacers are disposed on respective ones of the first and second sidewalls of the gate electrode. The first and second sidewall spacers have different dielectric constants. The first and second sidewall spacers may be substantially symmetrical and/or have substantially the same thickness.

Abstract translation: 诸如DRAM，SRAM或非易失性存储器件的存储器件包括衬底，设置在衬底上的栅极电极以及与栅电极相邻的第一和第二侧壁相邻的衬底中的源极和漏极区域。 第一和第二侧壁间隔物设置在栅电极的第一和第二侧壁的相应的一个上。 第一和第二侧壁间隔物具有不同的介电常数。 第一和第二侧壁间隔物可以是基本对称的和/或具有基本相同的厚度。

公开(公告)号：US07105917B2

公开(公告)日：2006-09-12

申请号：US09952645

申请日：2001-09-13

Applicant: Kang-Sik Cho ,  Chul-Sung Park ,  Gyu-Chul Kim

Inventor： Kang-Sik Cho ,  Chul-Sung Park ,  Gyu-Chul Kim

IPC: H01L23/02

CPC classification number: H01L23/5258 ,  H01L2224/13

Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device has a probing pad formed on a chip. The probing pad is connected to an output pad and an internal circuit though a fuse. After an electrical testing of the chip by the probing pad, the fuse is cut by a laser beam. Therefore, the probing pad is disconnected from the output pad and the internal circuit. The output pad is connected to an output lead of a package, which is encapsulating the chip. According to the device and the fabrication methods thereof, performance of the device can be enhanced by a low parasitic capacitance and a low parasitic resistance.

公开(公告)号：US20050051852A1

公开(公告)日：2005-03-10

申请号：US10911907

申请日：2004-08-05

Applicant: Gyu-chul Kim ,  Sung-bong Kim

Inventor： Gyu-chul Kim ,  Sung-bong Kim

IPC: H01L27/108 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L21/8244 ,  H01L21/8247 ,  H01L27/11 ,  H01L27/115 ,  H01L29/49 ,  H01L29/76 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/4983 ,  H01L21/28273 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/11 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7835 ,  Y10S257/90

Abstract: A memory device, such as a DRAM, SRAM or non-volatile memory device, includes a substrate, a gate electrode disposed on the substrate, and source and drain regions in the substrate adjacent respective first and second sidewalls of the gate electrode. First and second sidewall spacers are disposed on respective ones of the first and second sidewalls of the gate electrode. The first and second sidewall spacers have different dielectric constants. The first and second sidewall spacers may be substantially symmetrical and/or have substantially the same thickness.

Abstract translation: 诸如DRAM，SRAM或非易失性存储器件的存储器件包括衬底，设置在衬底上的栅极电极以及与栅电极相邻的第一和第二侧壁相邻的衬底中的源极和漏极区域。 第一和第二侧壁间隔物设置在栅电极的第一和第二侧壁的相应的一个上。 第一和第二侧壁间隔物具有不同的介电常数。 第一和第二侧壁间隔物可以是基本对称的和/或具有基本相同的厚度。

公开(公告)号：US20050012157A1

公开(公告)日：2005-01-20

申请号：US10892588

申请日：2004-07-15

Applicant: Man-Hyoung Ryoo ,  Gi-Sung Yeo ,  Si-Hyeung Lee ,  Gyu-Chul Kim ,  Sung-Gon Jung ,  Chang-Min Park ,  Hoo-Sung Cho

Inventor： Man-Hyoung Ryoo ,  Gi-Sung Yeo ,  Si-Hyeung Lee ,  Gyu-Chul Kim ,  Sung-Gon Jung ,  Chang-Min Park ,  Hoo-Sung Cho

IPC: G11C11/34 ,  G11C11/412 ,  H01L27/02 ,  H01L27/11

CPC classification number: H01L27/088 ,  G11C11/412 ,  H01L27/0203 ,  H01L27/1104 ,  Y10S257/903

Abstract: According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.

Abstract translation: 根据本发明的一些实施例，提供掺杂有P型杂质的衬底。 在衬底中掺杂N型杂质以将衬底分成P型杂质区和N型杂质区。 在P型和N型杂质区中形成具有第一间距的有源图案。 具有第二间距的栅极图案在与有源图案基本垂直的方向上形成在有源图案上。 描述和要求保护其他实施例。