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    Semiconductor memory device having a three-dimensional cell array structure
    2.
    发明申请
    Semiconductor memory device having a three-dimensional cell array structure 有权
    具有三维单元阵列结构的半导体存储器件

    公开(公告)号：US20080112209A1

    公开(公告)日：2008-05-15

    申请号：US11755329

    申请日：2007-05-30

    申请人： Woo-Yeong Cho ,  Sang-Beom Kang ,  Du-Eung Kim

    发明人： Woo-Yeong Cho ,  Sang-Beom Kang ,  Du-Eung Kim

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0023 ,  G11C11/1655 ,  G11C11/1657 ,  G11C13/0004 ,  G11C2213/71 ,  G11C2213/72

    摘要： A semiconductor memory device includes a plurality of cell array layers including a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction that intersects the first direction, and a plurality of memory cells disposed at intersections of the word lines and the bit lines. Each of the word lines has a word line position, each of the bit lines has a bit line position, and each of the memory cells includes a variable resistance device in series with a diode. The cell array layers are arranged in layers in a third direction that is perpendicular to the first and second directions. The bit lines of each of the cell array layers having a same bit line position are connected to a common column selector transistor, or the word lines of the cell array layers having a same word line position are connected to a common word line driver.

    摘要翻译： 半导体存储器件包括多个单元阵列层，包括沿第一方向延伸的多个字线，沿与第一方向相交的第二方向延伸的多个位线，以及设置在第一方向的交点处的多个存储单元 字线和位线。 每个字线具有字线位置，每个位线具有位线位置，并且每个存储单元包括与二极管串联的可变电阻器件。 单元阵列层在垂直于第一和第二方向的第三方向上排列成层。 具有相同位线位置的每个单元阵列层的位线连接到公共列选择晶体管，或者具有相同字线位置的单元阵列层的字线连接到公共字线驱动器。

    Phase change memory devices employing cell diodes and methods of fabricating the same
    5.
    发明申请
    Phase change memory devices employing cell diodes and methods of fabricating the same 有权
    使用单元二极管的相变存储器件及其制造方法

    公开(公告)号：US20060186483A1

    公开(公告)日：2006-08-24

    申请号：US11324112

    申请日：2005-12-30

    申请人： Woo-Yeong Cho ,  Du-Eung Kim ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Sang-Beom Kang ,  Beak-Hyung Cho ,  Choong-Keun Kwak

    发明人： Woo-Yeong Cho ,  Du-Eung Kim ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Sang-Beom Kang ,  Beak-Hyung Cho ,  Choong-Keun Kwak

    IPC分类号： H01L29/76

    CPC分类号： G11C13/0004 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

    摘要： Phase change memory devices having cell diodes and related methods are provided, where the phase change memory devices include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate, the word lines have a second conductivity type different from the first conductivity type and have substantially flat top surfaces, a plurality of first semiconductor patterns are one-dimensionally arrayed on each word line along a length direction of the word line, the first semiconductor patterns have the first conductivity type or the second conductivity type, second semiconductor patterns having the first conductivity type are stacked on the first semiconductor patterns, an insulating layer is provided on the substrate having the second semiconductor patterns, the insulating layer fills gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns, a plurality of phase change material patterns are two-dimensionally arrayed on the insulating layer, and the phase change material patterns are electrically connected to the second semiconductor patterns, respectively.

    摘要翻译： 提供具有单元二极管和相关方法的相变存储器件，其中相变存储器件包括第一导电类型的半导体衬底和设置在半导体衬底上的多个平行字线，字线具有不同的第二导电类型 从第一导电类型并且具有基本上平坦的顶表面，沿着字线的长度方向在每个字线上一维地排列多个第一半导体图案，第一半导体图案具有第一导电类型或第二导电类型 具有第一导电类型的第二半导体图案堆叠在第一半导体图案上，在具有第二半导体图案的基板上设置绝缘层，绝缘层填充字线之间的间隙区域，第一半导体图案之间的间隙区域和 第二半导体之间的间隙区域 多个相变材料图案被二维排列在绝缘层上，并且相变材料图案分别电连接到第二半导体图案。

    Semiconductor memory device having a three-dimensional cell array structure
    6.
    发明授权
    Semiconductor memory device having a three-dimensional cell array structure 有权
    具有三维单元阵列结构的半导体存储器件

    公开(公告)号：US07570511B2

    公开(公告)日：2009-08-04

    申请号：US11755329

    申请日：2007-05-30

    申请人： Woo-Yeong Cho ,  Sang-Beom Kang ,  Du-Eung Kim

    发明人： Woo-Yeong Cho ,  Sang-Beom Kang ,  Du-Eung Kim

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0023 ,  G11C11/1655 ,  G11C11/1657 ,  G11C13/0004 ,  G11C2213/71 ,  G11C2213/72

    摘要： A semiconductor memory device includes a plurality of cell array layers including a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction that intersects the first direction, and a plurality of memory cells disposed at intersections of the word lines and the bit lines. Each of the word lines has a word line position, each of the bit lines has a bit line position, and each of the memory cells includes a variable resistance device in series with a diode. The cell array layers are arranged in layers in a third direction that is perpendicular to the first and second directions. The bit lines of each of the cell array layers having a same bit line position are connected to a common column selector transistor, or the word lines of the cell array layers having a same word line position are connected to a common word line driver.

    摘要翻译： 半导体存储器件包括多个单元阵列层，包括沿第一方向延伸的多个字线，沿与第一方向相交的第二方向延伸的多个位线，以及设置在第一方向的交点处的多个存储单元 字线和位线。 每个字线具有字线位置，每个位线具有位线位置，并且每个存储单元包括与二极管串联的可变电阻器件。 单元阵列层在垂直于第一和第二方向的第三方向上排列成层。 具有相同位线位置的每个单元阵列层的位线连接到公共列选择晶体管，或者具有相同字线位置的单元阵列层的字线连接到公共字线驱动器。

    PHASE CHANGE MEMORY DEVICES EMPLOYING CELL DIODES AND METHODS OF FABRICATING THE SAME
    7.
    发明申请
    PHASE CHANGE MEMORY DEVICES EMPLOYING CELL DIODES AND METHODS OF FABRICATING THE SAME 有权
    使用单元的相变存储器件及其制造方法

    公开(公告)号：US20080303016A1

    公开(公告)日：2008-12-11

    申请号：US12196137

    申请日：2008-08-21

    申请人： Woo-Yeong Cho ,  Du-Eung Kim ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Sang-Beom Kang ,  Beak-Hyung Cho ,  Choong-Keun Kwak

    发明人： Woo-Yeong Cho ,  Du-Eung Kim ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Sang-Beom Kang ,  Beak-Hyung Cho ,  Choong-Keun Kwak

    IPC分类号： H01L45/00

    CPC分类号： G11C13/0004 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

    摘要： Phase change memory devices having cell diodes and related methods are provided, where the phase change memory devices include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate, the word lines have a second conductivity type different from the first conductivity type and have substantially flat top surfaces, a plurality of first semiconductor patterns are one-dimensionally arrayed on each word line along a length direction of the word line, the first semiconductor patterns have the first conductivity type or the second conductivity type, second semiconductor patterns having the first conductivity type are stacked on the first semiconductor patterns, an insulating layer is provided on the substrate having the second semiconductor patterns, the insulating layer fills gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns, a plurality of phase change material patterns are two-dimensionally arrayed on the insulating layer, and the phase change material patterns are electrically connected to the second semiconductor patterns, respectively.

    摘要翻译： 提供具有单元二极管和相关方法的相变存储器件，其中相变存储器件包括第一导电类型的半导体衬底和设置在半导体衬底上的多个平行字线，字线具有不同的第二导电类型 从第一导电类型并且具有基本上平坦的顶表面，沿着字线的长度方向在每个字线上一维地排列多个第一半导体图案，第一半导体图案具有第一导电类型或第二导电类型 具有第一导电类型的第二半导体图案堆叠在第一半导体图案上，在具有第二半导体图案的基板上设置绝缘层，绝缘层填充字线之间的间隙区域，第一半导体图案之间的间隙区域和 第二半导体之间的间隙区域 多个相变材料图案被二维排列在绝缘层上，并且相变材料图案分别电连接到第二半导体图案。

    Phase change memory devices employing cell diodes and methods of fabricating the same
    8.
    发明授权
    Phase change memory devices employing cell diodes and methods of fabricating the same 有权
    使用单元二极管的相变存储器件及其制造方法

    公开(公告)号：US07427531B2

    公开(公告)日：2008-09-23

    申请号：US11324112

    申请日：2005-12-30

    申请人： Woo-Yeong Cho ,  Du-Eung Kim ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Sang-Beom Kang ,  Beak-Hyung Cho ,  Choong-Keun Kwak

    发明人： Woo-Yeong Cho ,  Du-Eung Kim ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Sang-Beom Kang ,  Beak-Hyung Cho ,  Choong-Keun Kwak

    IPC分类号： H01L21/06

    CPC分类号： G11C13/0004 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

    摘要： Phase change memory devices having cell diodes and related methods are provided, where the phase change memory devices include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate, the word lines have a second conductivity type different from the first conductivity type and have substantially flat top surfaces, a plurality of first semiconductor patterns are one-dimensionally arrayed on each word line along a length direction of the word line, the first semiconductor patterns have the first conductivity type or the second conductivity type, second semiconductor patterns having the first conductivity type are stacked on the first semiconductor patterns, an insulating layer is provided on the substrate having the second semiconductor patterns, the insulating layer fills gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns, a plurality of phase change material patterns are two-dimensionally arrayed on the insulating layer, and the phase change material patterns are electrically connected to the second semiconductor patterns, respectively.

    摘要翻译： 提供具有单元二极管和相关方法的相变存储器件，其中相变存储器件包括第一导电类型的半导体衬底和设置在半导体衬底上的多个平行字线，字线具有不同的第二导电类型 从第一导电类型并且具有基本上平坦的顶表面，沿着字线的长度方向在每个字线上一维地排列多个第一半导体图案，第一半导体图案具有第一导电类型或第二导电类型 具有第一导电类型的第二半导体图案堆叠在第一半导体图案上，在具有第二半导体图案的基板上设置绝缘层，绝缘层填充字线之间的间隙区域，第一半导体图案之间的间隙区域和 第二半导体之间的间隙区域 多个相变材料图案被二维排列在绝缘层上，并且相变材料图案分别电连接到第二半导体图案。

    Memory cell array biasing method and a semiconductor memory device
    9.
    发明授权
    Memory cell array biasing method and a semiconductor memory device 有权
    存储单元阵列偏置方法和半导体存储器件

    公开(公告)号：US07317655B2

    公开(公告)日：2008-01-08

    申请号：US11327967

    申请日：2006-01-09

    申请人： Beak-Hyung Cho ,  Du-Eung Kim ,  Choong-Keun Kwak ,  Sang-Beom Kang ,  Woo-Yeong Cho ,  Hyung-Rok Oh

    发明人： Beak-Hyung Cho ,  Du-Eung Kim ,  Choong-Keun Kwak ,  Sang-Beom Kang ,  Woo-Yeong Cho ,  Hyung-Rok Oh

    IPC分类号： G11C8/00

    CPC分类号： G11C13/0004 ,  G11C11/5678 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/72

    摘要： A method of biasing a memory cell array during a data writing operation and a semiconductor memory device are provided. The semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line among a plurality of first lines and a second terminal of a memory cell is connected to a corresponding second line among a plurality of second lines; and a bias circuit for biasing a selected second line to a first voltage and non-selected second lines to a second voltage.

    摘要翻译： 提供了一种在数据写入操作期间偏置存储单元阵列的方法和半导体存储器件。 半导体存储器件包括：存储单元阵列，其包括多个存储单元，其中存储单元的第一端子连接到多条第一线路中的相应第一线路，而存储器单元的第二端子连接到 多个第二行中的对应的第二行; 以及用于将所选择的第二线偏压到第一电压和未选择的第二线到第二电压的偏置电路。