公开(公告)号：US20240321793A1

公开(公告)日：2024-09-26

申请号：US18125660

申请日：2023-03-23

Applicant: XILINX, INC.

Inventor： Yun WU ,  Henley LIU ,  Myongseob KIM ,  Chris LEE ,  Cheang Whang CHANG

IPC: H01L23/00

CPC classification number: H01L24/06 ,  H01L24/05 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/06132 ,  H01L2224/06177 ,  H01L2224/06179 ,  H01L2224/16227 ,  H01L2924/381 ,  H01L2924/3841

Abstract: An integrated circuit (IC) die includes a body having a dielectric layer and a plurality of contact pads formed on the dielectric layer. The IC die also includes a passivation layer disposed on the dielectric layer. The passivation layer has a plurality of openings exposing the plurality of contact pads. A plurality of inner under-bump-metallurgy (“UBM”) structures are disposed on a first portion of the plurality of openings, and a plurality of outer UBM structures are disposed on a second portion of the plurality of openings. The plurality of inner UBM structures have uniform spacing in a direction parallel to an edge of the body. The plurality of outer UBM structures are positioned around the plurality of inner UBM structures, and each of the plurality of outer UBM structures having a longitudinal axis directed toward a central area of the IC die.

公开(公告)号：US20230140675A1

公开(公告)日：2023-05-04

申请号：US17515354

申请日：2021-10-29

Applicant: XILINX, INC.

Inventor： Myongseob KIM ,  Henley LIU ,  Cheang Whang CHANG

IPC: H01L25/065 ,  H01L21/66 ,  H01L23/00

Abstract: An integrated circuit (IC) device is disclosed which includes at least a first hybrid bond interface layer disposed between adjacent wafers of a wafer stack. Routing within the hybrid bond interface layer allows test pads exposed on a top wafer of the wafer stack to electrically couple test keys within the wafer stack. By utilizing the routing within the hybrid bond interface layer to index electrical connections between adjacent wafers, IC dies stacked on the wafers may be fabricated with less mask sets as compared to conventional designs.

公开(公告)号：US20250149390A1

公开(公告)日：2025-05-08

申请号：US18941912

申请日：2024-11-08

Applicant: XILINX, INC.

Inventor： Andy WIDJAJA ,  Lik Huay LIM ,  Henley LIU ,  Jane Wang SOWARDS ,  Mohsen H. MARDI

IPC: H01L21/66 ,  H01L23/00 ,  H01L25/065

Abstract: Methods for fabricating an integrated circuit (IC) device, an IC die configured for probe testing, and an IC device are described therein. In one example, the method includes: forming a conductive cap above and in electrical contact with two or more of a pillars, each pillar coupled to a power contact pads of an IC die, removing the cap after testing; and depositing a hybrid bonding layer over the IC die device, the hybrid bonding layer having hybrid bond pads coupled the plurality of power contact pads and the signal contact pads of the IC die.

公开(公告)号：US20210265312A1

公开(公告)日：2021-08-26

申请号：US16798267

申请日：2020-02-21

Applicant: XILINX, INC.

Inventor： Myongseob KIM ,  Henley LIU ,  Cheang Whang CHANG

IPC: H01L25/065 ,  H01L21/50 ,  H01L25/00

Abstract: An integrated circuit device and techniques for manufacturing the same are described therein. The integrated circuit device leverages two or more pairs of stacked integrated circuit dies that are fabricated in mirror images to reduce the complexity of manufacturing, thus reducing cost. In one example, an integrated circuit device is provided that includes an integrated circuit (IC) die stack. The IC die stack includes first, second, third and fourth IC dies. The first and second IC dies are coupled by their active sides and include arrangements of integrated circuitry that are mirror images of each other. The third and fourth IC dies are also coupled by their active sides and include arrangements of integrated circuitry that are mirror images of each other.

公开(公告)号：US20240145411A1

公开(公告)日：2024-05-02

申请号：US17977632

申请日：2022-10-31

Applicant: XILINX, INC.

Inventor： Myongseob KIM ,  Henley LIU ,  Cheang-whang CHANG

IPC: H01L23/00 ,  G06F21/87

CPC classification number: H01L23/576 ,  G06F21/87

Abstract: Integrated circuit (IC) protections that prevent exposure or examination of integrated circuitry through backside analysis include a layer or mesh of an electrically conductive, electromagnetic radiation blocking material disposed over a backside of an IC device to prevent backside analysis. An electrically conductive conduit couples the material to a node of the integrated circuitry to provide a signal and/or voltage reference to the node through the layer/mesh. If the layer/mesh is tampered with, the integrated circuitry loses the voltage reference or signal thereby disabling the integrated circuitry. The IC device may include detection circuitry to monitor the node and to generate an alert and/or disable the circuitry upon tampering. The IC device may further include a support substrate, where a substrate between the material/mesh and the integrated circuitry is sufficiently thin that the IC device would be mechanically weak if the support substrate were removed.

公开(公告)号：US20240038556A1

公开(公告)日：2024-02-01

申请号：US17875226

申请日：2022-07-27

Applicant: XILINX, INC.

Inventor： Myongseob KIM ,  Henley LIU ,  Cheang-whang CHANG

IPC: H01L21/67 ,  H01L21/66 ,  H01L25/065

CPC classification number: H01L21/67288 ,  H01L21/67253 ,  H01L22/12 ,  H01L25/0657

Abstract: Methods for mitigating warpage on stacked wafers are provided herein. In one example, a method for mitigating warpage on stacked wafers includes depositing a first warpage compensating layer on a backside of a first wafer, stacking an active side of the first wafer on an active side of a second wafer to form a wafer stack having circuitry of the first wafer electrically connected to circuitry of the second wafer, and removing the first warpage compensating layer from the backside of the first wafer prior dicing the wafer stack.