公开(公告)号：US11824548B2

公开(公告)日：2023-11-21

申请号：US17555212

申请日：2021-12-17

Applicant: XILINX, INC.

Inventor： Shaojun Ma ,  Chi Fung Poon

IPC: H03L7/099 ,  G06F1/06 ,  H03K17/687

CPC classification number: H03L7/0995 ,  G06F1/06 ,  H03K17/6872 ,  H03K17/6874

Abstract: A multiplication injection locked oscillator (MIILO) circuitry includes a ring injection locked oscillator (ILO) circuitry that outputs clock signals, a first switching circuitry and a second switching circuitry. The ring ILO circuitry includes a first path having first delay stages, and a second path having a second delay stages. The first switching circuitry is connected to the first path and a voltage supply node. The first switching circuitry receives a first control signal and a second control signal and selectively connects the voltage supply node to the first path. The second switching circuitry is connected to the second path and a reference voltage node. The second switching circuitry receives the first control signal and the second control signal and selectively connects the reference voltage node to the second path.

公开(公告)号：US11728962B2

公开(公告)日：2023-08-15

申请号：US17644066

申请日：2021-12-13

Applicant: XILINX, INC.

Inventor： Shaojun Ma ,  Chi Fung Poon ,  Kevin Zheng ,  Parag Upadhyaya

IPC: H04L7/00 ,  H03K19/21

CPC classification number: H04L7/0037 ,  H03K19/21

Abstract: Clock generation circuitry includes quadrature locked loop circuitry having first injection locked oscillator circuitry, second injection locked oscillator circuitry, and XOR circuitry. The first injection locked oscillator circuitry receives a first input signal and a second input signal and outputs first clock signals. The first input signal and the second input signal correspond to a reference clock signal. The second injection locked oscillator circuitry is coupled to outputs of the first injection locked oscillator circuitry, and receives the first clock signals and generates second clock signals. The XOR circuitry receives the second clock signals and generates a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal. The frequencies of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are greater than the frequency of the reference clock signal.

公开(公告)号：US11108401B2

公开(公告)日：2021-08-31

申请号：US16688130

申请日：2019-11-19

Applicant: Xilinx, Inc.

Inventor： Jaewook Shin ,  Parag Upadhyaya ,  Shaojun Ma

IPC: H03L7/24 ,  H03K3/03 ,  H03L7/099 ,  G06F1/08 ,  H03B5/12 ,  H04L7/033 ,  H03L7/083 ,  H04L27/00 ,  H03F3/24 ,  H03F3/21

Abstract: A quadrature clock generator is disclosed. The quadrature clock generator may include a first injection-locked oscillator, a phase interpolator, and a second injection-locked oscillator. The first injection-locked oscillator may generate a first plurality clock signals from a first reference clock signal. The phase interpolator may generate a second reference clock signal from the first plurality of clock signals, and the second injection-locked oscillator may generate a second plurality of clock signals from the second reference clock signal. A first quadrature clock signal may be selected from the first plurality of clock signals and a second quadrature clock signal may be selected from the second plurality of reference clock signals.

公开(公告)号：US10270450B1

公开(公告)日：2019-04-23

申请号：US16110937

申请日：2018-08-23

Applicant: Xilinx, Inc.

Inventor： Shaojun Ma ,  Parag Upadhyaya ,  Didem Z. Turker Melek

IPC: H03K19/0185 ,  H03H11/28 ,  H03K19/0175 ,  H04B3/04 ,  H03K17/0812 ,  H03K19/018 ,  H04B1/04

Abstract: Methods and apparatus relate to a bidirectional differential interface having a voltage-mode transmit driver architecture formed of multiple selectively enabled slices for coarse output resistance impedance matching. In an illustrative example, the transmit driver may include a programmable resistance for fine-tuning to impedance match the output resistance for transmit operation. During receive operation, protective voltage may be proactively applied to gates of drive transistors, for example, to minimize voltage stresses applied by external signal sources. Some implementations may automatically float the sources of the drive transistors, for example, to prevent back-feeding externally driven signal currents during receive mode operations. The transmit driver may have programmable voltage swing on, for example, the upper and/or lower bounds to enhance compatibility. A programmable common mode voltage node may be selectively applied, for example, through common mode resistors for receive mode operations. Various embodiments may reduce pin count for high speed bidirectional I/O.