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    Unified low power bidirectional port
    1.
    发明授权
    Unified low power bidirectional port 有权

    公开(公告)号：US10270450B1

    公开(公告)日：2019-04-23

    申请号：US16110937

    申请日：2018-08-23

    申请人： Xilinx, Inc.

    发明人： Shaojun Ma ,  Parag Upadhyaya ,  Didem Z. Turker Melek

    IPC分类号： H03K19/0185 ,  H03H11/28 ,  H03K19/0175 ,  H04B3/04 ,  H03K17/0812 ,  H03K19/018 ,  H04B1/04

    摘要： Methods and apparatus relate to a bidirectional differential interface having a voltage-mode transmit driver architecture formed of multiple selectively enabled slices for coarse output resistance impedance matching. In an illustrative example, the transmit driver may include a programmable resistance for fine-tuning to impedance match the output resistance for transmit operation. During receive operation, protective voltage may be proactively applied to gates of drive transistors, for example, to minimize voltage stresses applied by external signal sources. Some implementations may automatically float the sources of the drive transistors, for example, to prevent back-feeding externally driven signal currents during receive mode operations. The transmit driver may have programmable voltage swing on, for example, the upper and/or lower bounds to enhance compatibility. A programmable common mode voltage node may be selectively applied, for example, through common mode resistors for receive mode operations. Various embodiments may reduce pin count for high speed bidirectional I/O.

    Multi-port inductors and transformers for accurately predicting voltage-controlled oscillator (VCO) frequency
    4.
    发明授权
    Multi-port inductors and transformers for accurately predicting voltage-controlled oscillator (VCO) frequency 有权

    公开(公告)号：US10715153B1

    公开(公告)日：2020-07-14

    申请号：US16517103

    申请日：2019-07-19

    申请人： XILINX, INC.

    发明人： Adebabay M. Bekele ,  Parag Upadhyaya ,  Didem Z. Turker Melek ,  Jing Jing

    IPC分类号： H03L7/099 ,  H03C3/09 ,  H03L7/183

    摘要： Apparatus and associated methods relate to automatically generating a data structure representation of an on-chip inductive-capacitive (LC) tank circuit by determining parasitic inductances in each of the segments of conductive paths that connect a main inductor to one or more selectable VCO components such as capacitors and varactors, for example. In an illustrative example, one or more of the selectable VCO components may be arranged, when selected, to form a parallel resonant LC tank with the main inductor. A method may include defining nodes ai terminating each of the segments along the conductive paths between the main inductor terminals and a drive circuit. By modelling the paths as multi-port inductors and transformers, resonant frequency of the VCO may be more accurately predicted by simulation.

    On-chip noise measurement
    5.
    发明授权
    On-chip noise measurement 有权
    片内噪声测量

    公开(公告)号：US08928334B1

    公开(公告)日：2015-01-06

    申请号：US13722800

    申请日：2012-12-20

    申请人： Xilinx, Inc.

    发明人： Mayank Raj ,  Didem Z. Turker Melek

    IPC分类号： G01R29/26

    CPC分类号： G01R29/26 ,  G01R31/31708

    摘要： An apparatus relating to on-chip noise measurement is disclosed. In such an apparatus, an asynchronous comparator receives a first input and a second input to provide a digital output. A threshold voltage generator receives a first periodic signal and a second periodic signal to provide the second input as an analog voltage responsive to the first and second periodic signals. A sampling circuit is coupled to receive the digital output signal and a third periodic signal. The sampling circuit is configured to sample the digital output signal using the third periodic signal to provide a sampled signal of the digital output signal. A processor is coupled to receive a delay signal and the sampled signal to determine a noise measurement signal for the first input signal.

    摘要翻译： 公开了一种与片上噪声测量相关的装置。 在这种装置中，异步比较器接收第一输入和第二输入以提供数字输出。 阈值电压发生器接收第一周期信号和第二周期信号，以响应于第一和第二周期信号将第二输入提供为模拟电压。 一个采样电路被耦合以接收数字输出信号和第三周期信号。 采样电路被配置为使用第三周期信号对数字输出信号进行采样，以提供数字输出信号的采样信号。 耦合处理器以接收延迟信号和采样信号以确定用于第一输入信号的噪声测量信号。

    RECONFIGURABLE FRACTIONAL-N FREQUENCY GENERATION FOR A PHASE-LOCKED LOOP
    7.
    发明申请
    RECONFIGURABLE FRACTIONAL-N FREQUENCY GENERATION FOR A PHASE-LOCKED LOOP 审中-公开
    用于相位锁定环路的可重构分段N频率生成

    公开(公告)号：US20160322979A1

    公开(公告)日：2016-11-03

    申请号：US14700695

    申请日：2015-04-30

    申请人： Xilinx, Inc.

    发明人： Parag Upadhyaya ,  Adebabay M. Bekele ,  Didem Z. Turker Melek ,  Zhaoyin D. Wu

    IPC分类号： H03L7/095 ,  H04B1/50 ,  H03M3/00

    CPC分类号： H03L7/095 ,  H03L7/18 ,  H03L7/197 ,  H03L7/1974 ,  H03M3/30 ,  H04B1/50

    摘要： In an example, a phase-locked loop (PLL) circuit includes an error detector operable to generate an error signal; an oscillator operable to provide an output signal having an output frequency based on the error signal and a frequency band select signal, the output frequency being a frequency multiplier times a reference frequency; a frequency divider operable to divide the output frequency of the output signal to generate a feedback signal based on a divider control signal; a sigma-delta modulator (SDM) operable to generate the divider control signal based on inputs indicative of an integer value and a fractional value of the frequency multiplier, the SDM responsive to an order select signal operable to select an order of the SDM; and a state machine operable to, in an acquisition state, generate the frequency band select signal and set the order of the SDM.

    摘要翻译： 在一个示例中，锁相环（PLL）电路包括可操作以产生误差信号的误差检测器; 振荡器，其可操作以提供具有基于所述误差信号和频带选择信号的输出频率的输出信号，所述输出频率是频率乘数乘以参考频率; 分频器，用于将输出信号的输出频率除以基于分频器控制信号产生反馈信号; Σ-Δ调制器（SDM），可操作以基于表示所述倍频器的整数值和分数值的输入产生所述除法器控制信号，所述SDM响应于可操作以选择所述SDM的次序的订单选择信号; 以及状态机，其可操作以在获取状态下生成所述频带选择信号并设置所述SDM的顺序。

    Programmable digital sigma delta modulator
    9.
    发明授权
    Programmable digital sigma delta modulator 有权

    公开(公告)号：US10348310B1

    公开(公告)日：2019-07-09

    申请号：US15992646

    申请日：2018-05-30

    申请人： Xilinx, Inc.

    发明人： Karim M. Megawer ,  Parag Upadhyaya ,  Didem Z. Turker Melek ,  Zhaoyin D. Wu

    IPC分类号： H03L7/08 ,  H03M3/00 ,  H03L7/197

    摘要： An example sigma delta modulator (SDM) circuit includes a floor circuit, a subtractor having a first input coupled an input of the floor circuit and a second input coupled to an output of the floor circuit, and a multi-stage noise shaping (MASH) converter having a programmable order. The MASH converter includes an input coupled to an output of the subtractor. The SDM further includes a programmable delay circuit having an input coupled to the output of the floor circuit, and an adder having a first input coupled to an output of the MASH converter and a second input coupled to an output of the programmable delay circuit.

    Data reception with feedback equalization for high and low data rates
    10.
    发明授权
    Data reception with feedback equalization for high and low data rates 有权
    数据接收，反馈均衡，高，低数据速率

    公开(公告)号：US09237041B1

    公开(公告)日：2016-01-12

    申请号：US14601587

    申请日：2015-01-21

    申请人： Xilinx, Inc.

    发明人： Fu-Tai An ,  Didem Z. Turker Melek ,  Yuan-Shih Chen

    IPC分类号： H04L27/18 ,  H04L25/03 ,  H04L7/00 ,  H04L1/00 ,  H04L25/02

    CPC分类号： H04L25/03057 ,  H04L1/0002 ,  H04L7/0025 ,  H04L7/0058 ,  H04L25/0292 ,  H04L25/03146 ,  H04L25/03885 ,  H04L2025/0349

    摘要： A method relates generally to data reception for any of a plurality of data rates. In such a method, information and phases of a clock signal are obtained by a decision feedback equalizer. The information is equalized using the phases of the clock signal with the decision feedback equalizer to provide equalized sample streams. The equalized sample streams and the phases of the clock signal are provided to a selection circuit block. A first and a second phase of the phases are swapped, along with swapping a first and a second equalized sample stream corresponding to the first phase and the second phase, responsive to a data rate of the plurality of data rates.

    摘要翻译： 一种方法一般涉及多种数据速率中的任一种的数据接收。 在这种方法中，通过判决反馈均衡器获得时钟信号的信息和相位。 使用具有判决反馈均衡器的时钟信号的相位来均衡信息以提供均衡的采样流。 均衡采样流和时钟信号的相位被提供给选择电路块。 交换相的第一和第二阶段，以及响应于多个数据速率的数据速率交换对应于第一相位和第二阶段的第一和第二均衡采样流。