公开(公告)号：US08656263B2

公开(公告)日：2014-02-18

申请号：US13118137

申请日：2011-05-27

申请人： Xinde Hu ,  Anthony D. Weathers ,  Richard D. Barndt

发明人： Xinde Hu ,  Anthony D. Weathers ,  Richard D. Barndt

IPC分类号： H03M13/00

CPC分类号： H03M13/256 ,  G06F11/1072 ,  H03M13/253 ,  H03M13/2933 ,  H03M13/3988

摘要： A method and system for storing data in a multi-level cell (MLC) flash memory device are described. The method includes receiving data for storage in the flash memory device, the flash memory device comprising an array of MLC flash memory cells, and encoding the received data into non-binary symbols according to a trellis-coded modulation scheme. The method further includes writing each of the non-binary symbols to a respective flash memory cell set, wherein each flash memory cell set comprises a plurality of MLC flash memory cells.

摘要翻译： 描述了用于在多级单元（MLC）闪速存储器件中存储数据的方法和系统。 所述方法包括接收用于存储在闪存设备中的数据，所述闪存设备包括MLC闪存单元阵列，并且根据网格编码的调制方案将接收到的数据编码为非二进制符号。 该方法还包括将每个非二进制符号写入相应的闪存单元组，其中每个快闪存储器单元组包括多个MLC闪存单元。

公开(公告)号：US08484519B2

公开(公告)日：2013-07-09

申请号：US13553707

申请日：2012-07-19

申请人： Anthony D. Weathers ,  Richard D. Barndt ,  Xinde Hu

发明人： Anthony D. Weathers ,  Richard D. Barndt ,  Xinde Hu

IPC分类号： G06F11/00 ,  G11C29/00 ,  H03M13/00

CPC分类号： G11C16/3459 ,  G06F11/076 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2211/5621

摘要： The subject disclosure describes a method for reducing a sector error rate in a flash memory device, the method comprising, identifying a first program verify level having a first value, selecting an adjustment value for the first program verify level and programming the adjustment value to the first program verify level to replace the first value and to shift a first programming distribution associated with the first program verify level, wherein the shift in the first programming distribution is associated with a decrease in a sector error rate, wherein the shift in the first programming distribution is associated with an increase in a bit error rate. A flash storage device and computer-readable media are also provided.

摘要翻译： 主题公开内容描述了一种用于减少闪存设备中的扇区错误率的方法，该方法包括：识别具有第一值的第一程序验证级别，为第一程序验证级别选择调整值，并将调整值编程为 第一程序验证电平以替换第一值并移动与第一程序验证电平相关联的第一编程分布，其中第一编程分布中的移位与扇区错误率的减小相关联，其中第一编程中的移位 分布与误码率的增加相关联。 还提供闪存存储设备和计算机可读介质。

公开(公告)号：US20130047045A1

公开(公告)日：2013-02-21

申请号：US13584698

申请日：2012-08-13

申请人： Xinde Hu ,  Anthony D. Weathers ,  Richard D. Barndt

发明人： Xinde Hu ,  Anthony D. Weathers ,  Richard D. Barndt

IPC分类号： H03M13/05 ,  G06F11/00

CPC分类号： G06F11/1048 ,  G11C2029/0411

摘要： The subject disclosure provides a method for generating a read-level error signal, comprising, correcting a plurality of bits read from a flash memory, determining a first error rate of a first error type corrected in the bits and determining a second error rate of a second error type corrected in the bits. In certain aspects, methods of the subject technology further provides steps for comparing the first error rate with the second error rate and generating a read-level error signal based on the comparison of the first error rate and the second error rate. A decoder and flash storage device are also provided.

摘要翻译： 本公开提供了一种用于生成读取级错误信号的方法，包括：校正从闪速存储器读取的多个位，确定在位中校正的第一错误类型的第一错误率，并确定第二错误率 在位中校正的第二个错误类型。 在某些方面，本发明技术的方法还提供了用于将第一错误率与第二错误率进行比较的步骤，并且基于第一错误率和第二错误率的比较来生成读取级错误信号。 还提供了解码器和闪存存储设备。

公开(公告)号：US20130047044A1

公开(公告)日：2013-02-21

申请号：US13553707

申请日：2012-07-19

申请人： Anthony D. Weathers ,  Richard D. Barndt ,  Xinde Hu

发明人： Anthony D. Weathers ,  Richard D. Barndt ,  Xinde Hu

IPC分类号： G06F11/07 ,  G06F11/00

CPC分类号： G11C16/3459 ,  G06F11/076 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2211/5621

摘要： The subject disclosure describes a method for reducing a sector error rate in a flash memory device, the method comprising, identifying a first program verify level having a first value, selecting an adjustment value for the first program verify level and programming the adjustment value to the first program verify level to replace the first value and to shift a first programming distribution associated with the first program verify level, wherein the shift in the first programming distribution is associated with a decrease in a sector error rate, wherein the shift in the first programming distribution is associated with an increase in a bit error rate. A flash storage device and computer-readable media are also provided.

摘要翻译： 主题公开内容描述了一种用于减少闪存设备中的扇区错误率的方法，该方法包括：识别具有第一值的第一程序验证级别，为第一程序验证级别选择调整值，并将调整值编程为 第一程序验证电平以替换第一值并移动与第一程序验证电平相关联的第一编程分布，其中第一编程分布中的移位与扇区错误率的减小相关联，其中第一编程中的移位 分布与误码率的增加相关联。 还提供闪存存储设备和计算机可读介质。

公开(公告)号：US08605501B2

公开(公告)日：2013-12-10

申请号：US13176727

申请日：2011-07-05

申请人： Xinde Hu ,  Richard D. Barndt ,  Anthony D. Weathers

发明人： Xinde Hu ,  Richard D. Barndt ,  Anthony D. Weathers

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C16/3454

摘要： Disclosed is an system and method for determining a probability that a memory cell was programmed to a certain input level. An output level is received from a memory cell and a probability is determined that the output level corresponds to each of a plurality of programming levels. Each probability is determined as a function of the output level, a mean value of a distribution corresponding to the programming level, and a variance from the mean value with the variance being determined by a relative position of the output level with respect to the mean value. A probability value is generated as a function of the plurality of determined probabilities and then provided for use at a demodulator.

摘要翻译： 公开了一种用于确定存储器单元被编程到某一输入电平的概率的系统和方法。 从存储器单元接收输出电平，并且确定输出电平对应于多个编程电平中的每一个的概率。 每个概率被确定为输出电平的函数，与编程电平相对应的分布的平均值，以及与方差的平均值的差异由输出电平相对于平均值的相对位置确定 。 生成概率值作为多个确定概率的函数，然后提供给解调器使用。

公开(公告)号：US20120240006A1

公开(公告)日：2012-09-20

申请号：US13118137

申请日：2011-05-27

申请人： Xinde Hu ,  Anthony D. Weathers ,  Richard D. Barndt

发明人： Xinde Hu ,  Anthony D. Weathers ,  Richard D. Barndt

IPC分类号： H03M13/15 ,  G06F11/16 ,  G06F11/08

CPC分类号： H03M13/256 ,  G06F11/1072 ,  H03M13/253 ,  H03M13/2933 ,  H03M13/3988

摘要： A method and system for storing data in a multi-level cell (MLC) flash memory device are described. The method includes receiving data for storage in the flash memory device, the flash memory device comprising an array of MLC flash memory cells, and encoding the received data into non-binary symbols according to a trellis-coded modulation scheme. The method further includes writing each of the non-binary symbols to a respective flash memory cell set, wherein each flash memory cell set comprises a plurality of MLC flash memory cells.

摘要翻译： 描述了用于在多级单元（MLC）闪速存储器件中存储数据的方法和系统。 所述方法包括接收用于存储在闪存设备中的数据，所述闪存设备包括MLC闪存单元阵列，并且根据网格编码的调制方案将接收到的数据编码为非二进制符号。 该方法还包括将每个非二进制符号写入相应的闪存单元组，其中每个快闪存储器单元组包括多个MLC闪存单元。

公开(公告)号：US08055973B2

公开(公告)日：2011-11-08

申请号：US12479652

申请日：2009-06-05

申请人： Shayan Srinivasa Garani ,  Nicholas J. Richardson ,  Xinde Hu ,  Sivagnanam Parthasarathy

发明人： Shayan Srinivasa Garani ,  Nicholas J. Richardson ,  Xinde Hu ,  Sivagnanam Parthasarathy

IPC分类号： H03M13/00

CPC分类号： H03M13/27 ,  G11B2020/10796 ,  G11B2020/185

摘要： An interleaver is constructed based on the joint constraints imposed in the channel and the code domains. A sequentially optimal algorithm is used for mapping bits in the inter-symbol interference (ISI) domain to the code domain by taking into account the ISI memory depth and the connectivity of the nodes within the parity check matrix. Primary design constraints are considered such as the parallelism factor so that the proposed system is hardware compliant in meeting high throughput requirements.

摘要翻译： 基于施加在信道和代码域中的联合约束来构造交织器。 通过考虑ISI存储器深度和奇偶校验矩阵内节点的连通性，使用顺序优化算法将码元间干扰（ISI）域中的比特映射到码域。 考虑了主要设计约束，例如并行因素，使得所提出的系统在满足高吞吐量要求方面符合硬件要求。

公开(公告)号：US20110078540A1

公开(公告)日：2011-03-31

申请号：US12610094

申请日：2009-10-30

申请人： Xinde Hu ,  Sivagnanam Parthasarathy ,  Shayan Srinivasa Garani ,  Anthony Weathers ,  Richard Barndt

发明人： Xinde Hu ,  Sivagnanam Parthasarathy ,  Shayan Srinivasa Garani ,  Anthony Weathers ,  Richard Barndt

IPC分类号： H03M13/05 ,  G06F11/10 ,  H03M13/27

CPC分类号： H03M13/1105 ,  G11B20/1833 ,  G11B2020/185 ,  G11B2220/2516 ,  H03M13/2707 ,  H03M13/2732 ,  H03M13/2957 ,  H03M13/3746 ,  H03M13/4146 ,  H03M13/6331 ,  H03M13/6516

摘要： To allow a single LDPC decoder to operate on both 512 B blocks and 4 KB blocks with comparable error correction performance, 512 KB blocks are interlaced to form a 1 KB data sequence, and four sequential 1 KB data sequences are concatenated to form a 4 KB sector. A de-interlacer between the detector and decoder forms multiple data sequence from a single data sequence output by the detector. The multiple data sequences are separately processed by a de-interleaver between the de-interlacer and the LDPC decoder, by the LDPC decoder, and by an interleaver at the output of the LDPD decoder. An interlacer recombines the multiple data sequences into a single output. Diversity may be improved by feeding interleaver seeds for respective codewords into the de-interleaver and interleaver during processing.

摘要翻译： 为了允许单个LDPC解码器在具有可比较纠错性能的512B块和4KB块上操作，512KB块被隔行扫描以形成1KB数据序列，并且连接四个连续的1KB数据序列以形成4KB 部门。 检测器和解码器之间的去隔行器从由检测器输出的单个数据序列形成多个数据序列。 多个数据序列由解交织器和LDPC解码器之间的解交织器，LDPC解码器和LDPD解码器的输出处的交织器分开处理。 隔行扫描器将多个数据序列重组为单个输出。 可以通过在处理期间将相应码字的交织器种子馈送到去交织器和交织器来改进分集。

公开(公告)号：US08255768B2

公开(公告)日：2012-08-28

申请号：US12610094

申请日：2009-10-30

申请人： Xinde Hu ,  Sivagnanam Parthasarathy ,  Shayan Srinivasa Garani ,  Anthony Weathers ,  Richard Barndt

发明人： Xinde Hu ,  Sivagnanam Parthasarathy ,  Shayan Srinivasa Garani ,  Anthony Weathers ,  Richard Barndt

IPC分类号： G06F11/00

CPC分类号： H03M13/1105 ,  G11B20/1833 ,  G11B2020/185 ,  G11B2220/2516 ,  H03M13/2707 ,  H03M13/2732 ,  H03M13/2957 ,  H03M13/3746 ,  H03M13/4146 ,  H03M13/6331 ,  H03M13/6516

摘要： To allow a single LDPC decoder to operate on both 512 B blocks and 4 KB blocks with comparable error correction performance, 512 KB blocks are interlaced to form a 1 KB data sequence, and four sequential 1 KB data sequences are concatenated to form a 4 KB sector. A de-interlacer between the detector and decoder forms multiple data sequence from a single data sequence output by the detector. The multiple data sequences are separately processed by a de-interleaver between the de-interlacer and the LDPC decoder, by the LDPC decoder, and by an interleaver at the output of the LDPD decoder. An interlacer recombines the multiple data sequences into a single output. Diversity may be improved by feeding interleaver seeds for respective codewords into the de-interleaver and interleaver during processing.

摘要翻译： 为了允许单个LDPC解码器在具有可比较纠错性能的512B块和4KB块上操作，512KB块被隔行扫描以形成1KB数据序列，并且四个连续的1KB数据序列被级联以形成4KB 部门。 检测器和解码器之间的去隔行器从由检测器输出的单个数据序列形成多个数据序列。 多个数据序列由解交织器和LDPC解码器之间的解交织器，LDPC解码器和LDPD解码器的输出处的交织器分开处理。 隔行扫描器将多个数据序列重组为单个输出。 可以通过在处理期间将相应码字的交织器种子馈送到去交织器和交织器来改进分集。

公开(公告)号：US08848438B2

公开(公告)日：2014-09-30

申请号：US13253029

申请日：2011-10-04

申请人： Xinde Hu

发明人： Xinde Hu

IPC分类号： G11C16/04 ,  G11C11/56 ,  G11C16/26

CPC分类号： G11C11/5642 ,  G11C16/26

摘要： Disclosed is an system and method for reading a flash memory cell with an adjusted read level. A current read level is adjusted to a new read level associated with increasing a first error rate to decrease a second error rate. The first error rate is associated with determining that the most significant bit of the flash memory cell is a binary 1 and the second error rate is associated with determining that the most significant bit is a binary 0. On reading the memory cell, a probability value is generated for the most significant bit, the probability being higher if the bit is equivalent to a binary 0 than if the bit is equivalent to a binary 1.

摘要翻译： 公开了一种用于读取具有调整读取电平的闪存单元的系统和方法。 当前读取电平被调整到与增加第一错误率相关联以减少第二错误率的新的读取级别。 第一错误率与确定闪速存储器单元的最高有效位是二进制1并且第二错误率与确定最高有效位是二进制0相关联。在读取存储器单元时，概率值 对于最高有效位产生，如果该位等于二进制0，则该概率高于如果该位等效于二进制1。