公开(公告)号：US08656263B2

公开(公告)日：2014-02-18

申请号：US13118137

申请日：2011-05-27

申请人： Xinde Hu ,  Anthony D. Weathers ,  Richard D. Barndt

发明人： Xinde Hu ,  Anthony D. Weathers ,  Richard D. Barndt

IPC分类号： H03M13/00

CPC分类号： H03M13/256 ,  G06F11/1072 ,  H03M13/253 ,  H03M13/2933 ,  H03M13/3988

摘要： A method and system for storing data in a multi-level cell (MLC) flash memory device are described. The method includes receiving data for storage in the flash memory device, the flash memory device comprising an array of MLC flash memory cells, and encoding the received data into non-binary symbols according to a trellis-coded modulation scheme. The method further includes writing each of the non-binary symbols to a respective flash memory cell set, wherein each flash memory cell set comprises a plurality of MLC flash memory cells.

摘要翻译： 描述了用于在多级单元（MLC）闪速存储器件中存储数据的方法和系统。 所述方法包括接收用于存储在闪存设备中的数据，所述闪存设备包括MLC闪存单元阵列，并且根据网格编码的调制方案将接收到的数据编码为非二进制符号。 该方法还包括将每个非二进制符号写入相应的闪存单元组，其中每个快闪存储器单元组包括多个MLC闪存单元。

公开(公告)号：US08484519B2

公开(公告)日：2013-07-09

申请号：US13553707

申请日：2012-07-19

申请人： Anthony D. Weathers ,  Richard D. Barndt ,  Xinde Hu

发明人： Anthony D. Weathers ,  Richard D. Barndt ,  Xinde Hu

IPC分类号： G06F11/00 ,  G11C29/00 ,  H03M13/00

CPC分类号： G11C16/3459 ,  G06F11/076 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2211/5621

摘要： The subject disclosure describes a method for reducing a sector error rate in a flash memory device, the method comprising, identifying a first program verify level having a first value, selecting an adjustment value for the first program verify level and programming the adjustment value to the first program verify level to replace the first value and to shift a first programming distribution associated with the first program verify level, wherein the shift in the first programming distribution is associated with a decrease in a sector error rate, wherein the shift in the first programming distribution is associated with an increase in a bit error rate. A flash storage device and computer-readable media are also provided.

摘要翻译： 主题公开内容描述了一种用于减少闪存设备中的扇区错误率的方法，该方法包括：识别具有第一值的第一程序验证级别，为第一程序验证级别选择调整值，并将调整值编程为 第一程序验证电平以替换第一值并移动与第一程序验证电平相关联的第一编程分布，其中第一编程分布中的移位与扇区错误率的减小相关联，其中第一编程中的移位 分布与误码率的增加相关联。 还提供闪存存储设备和计算机可读介质。

公开(公告)号：US08605501B2

公开(公告)日：2013-12-10

申请号：US13176727

申请日：2011-07-05

申请人： Xinde Hu ,  Richard D. Barndt ,  Anthony D. Weathers

发明人： Xinde Hu ,  Richard D. Barndt ,  Anthony D. Weathers

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C16/3454

摘要： Disclosed is an system and method for determining a probability that a memory cell was programmed to a certain input level. An output level is received from a memory cell and a probability is determined that the output level corresponds to each of a plurality of programming levels. Each probability is determined as a function of the output level, a mean value of a distribution corresponding to the programming level, and a variance from the mean value with the variance being determined by a relative position of the output level with respect to the mean value. A probability value is generated as a function of the plurality of determined probabilities and then provided for use at a demodulator.

摘要翻译： 公开了一种用于确定存储器单元被编程到某一输入电平的概率的系统和方法。 从存储器单元接收输出电平，并且确定输出电平对应于多个编程电平中的每一个的概率。 每个概率被确定为输出电平的函数，与编程电平相对应的分布的平均值，以及与方差的平均值的差异由输出电平相对于平均值的相对位置确定 。 生成概率值作为多个确定概率的函数，然后提供给解调器使用。

公开(公告)号：US20120240006A1

公开(公告)日：2012-09-20

申请号：US13118137

申请日：2011-05-27

申请人： Xinde Hu ,  Anthony D. Weathers ,  Richard D. Barndt

发明人： Xinde Hu ,  Anthony D. Weathers ,  Richard D. Barndt

IPC分类号： H03M13/15 ,  G06F11/16 ,  G06F11/08

CPC分类号： H03M13/256 ,  G06F11/1072 ,  H03M13/253 ,  H03M13/2933 ,  H03M13/3988

摘要： A method and system for storing data in a multi-level cell (MLC) flash memory device are described. The method includes receiving data for storage in the flash memory device, the flash memory device comprising an array of MLC flash memory cells, and encoding the received data into non-binary symbols according to a trellis-coded modulation scheme. The method further includes writing each of the non-binary symbols to a respective flash memory cell set, wherein each flash memory cell set comprises a plurality of MLC flash memory cells.

摘要翻译： 描述了用于在多级单元（MLC）闪速存储器件中存储数据的方法和系统。 所述方法包括接收用于存储在闪存设备中的数据，所述闪存设备包括MLC闪存单元阵列，并且根据网格编码的调制方案将接收到的数据编码为非二进制符号。 该方法还包括将每个非二进制符号写入相应的闪存单元组，其中每个快闪存储器单元组包括多个MLC闪存单元。

公开(公告)号：US20130047045A1

公开(公告)日：2013-02-21

申请号：US13584698

申请日：2012-08-13

申请人： Xinde Hu ,  Anthony D. Weathers ,  Richard D. Barndt

发明人： Xinde Hu ,  Anthony D. Weathers ,  Richard D. Barndt

IPC分类号： H03M13/05 ,  G06F11/00

CPC分类号： G06F11/1048 ,  G11C2029/0411

摘要： The subject disclosure provides a method for generating a read-level error signal, comprising, correcting a plurality of bits read from a flash memory, determining a first error rate of a first error type corrected in the bits and determining a second error rate of a second error type corrected in the bits. In certain aspects, methods of the subject technology further provides steps for comparing the first error rate with the second error rate and generating a read-level error signal based on the comparison of the first error rate and the second error rate. A decoder and flash storage device are also provided.

摘要翻译： 本公开提供了一种用于生成读取级错误信号的方法，包括：校正从闪速存储器读取的多个位，确定在位中校正的第一错误类型的第一错误率，并确定第二错误率 在位中校正的第二个错误类型。 在某些方面，本发明技术的方法还提供了用于将第一错误率与第二错误率进行比较的步骤，并且基于第一错误率和第二错误率的比较来生成读取级错误信号。 还提供了解码器和闪存存储设备。

公开(公告)号：US20130047044A1

公开(公告)日：2013-02-21

申请号：US13553707

申请日：2012-07-19

申请人： Anthony D. Weathers ,  Richard D. Barndt ,  Xinde Hu

发明人： Anthony D. Weathers ,  Richard D. Barndt ,  Xinde Hu

IPC分类号： G06F11/07 ,  G06F11/00

CPC分类号： G11C16/3459 ,  G06F11/076 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2211/5621

摘要： The subject disclosure describes a method for reducing a sector error rate in a flash memory device, the method comprising, identifying a first program verify level having a first value, selecting an adjustment value for the first program verify level and programming the adjustment value to the first program verify level to replace the first value and to shift a first programming distribution associated with the first program verify level, wherein the shift in the first programming distribution is associated with a decrease in a sector error rate, wherein the shift in the first programming distribution is associated with an increase in a bit error rate. A flash storage device and computer-readable media are also provided.

摘要翻译： 主题公开内容描述了一种用于减少闪存设备中的扇区错误率的方法，该方法包括：识别具有第一值的第一程序验证级别，为第一程序验证级别选择调整值，并将调整值编程为 第一程序验证电平以替换第一值并移动与第一程序验证电平相关联的第一编程分布，其中第一编程分布中的移位与扇区错误率的减小相关联，其中第一编程中的移位 分布与误码率的增加相关联。 还提供闪存存储设备和计算机可读介质。

公开(公告)号：US20120236651A1

公开(公告)日：2012-09-20

申请号：US13176727

申请日：2011-07-05

申请人： Xinde HU ,  Richard D. Barndt ,  Anthony D. Weathers

发明人： Xinde HU ,  Richard D. Barndt ,  Anthony D. Weathers

IPC分类号： G11C16/10

CPC分类号： G11C16/10 ,  G11C16/3454

摘要： Disclosed is an system and method for determining a probability that a memory cell was programmed to a certain input level. An output level is received from a memory cell and a probability is determined that the output level corresponds to each of a plurality of programming levels. Each probability is determined as a function of the output level, a mean value of a distribution corresponding to the programming level, and a variance from the mean value with the variance being determined by a relative position of the output level with respect to the mean value. A probability value is generated as a function of the plurality of determined probabilities and then provided for use at a demodulator.

摘要翻译： 公开了一种用于确定存储器单元被编程到某一输入电平的概率的系统和方法。 从存储器单元接收输出电平，并且确定输出电平对应于多个编程电平中的每一个的概率。 每个概率被确定为输出电平的函数，与编程电平相对应的分布的平均值，以及与方差的平均值的差异由输出电平相对于平均值的相对位置确定 。 生成概率值作为多个确定概率的函数，然后提供给解调器使用。

公开(公告)号：US08656256B2

公开(公告)日：2014-02-18

申请号：US13177482

申请日：2011-07-06

申请人： Anthony D. Weathers ,  Richard D. Barndt ,  Ashot Melik-Martirosian

发明人： Anthony D. Weathers ,  Richard D. Barndt ,  Ashot Melik-Martirosian

IPC分类号： G11C29/00 ,  G06F13/00 ,  G06F13/28 ,  G11C11/34 ,  G11C16/06 ,  G11C7/00

CPC分类号： G06F11/1072 ,  G11C11/5621 ,  G11C16/10 ,  G11C16/34 ,  G11C29/44 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2029/4402 ,  G11C2211/5641 ,  H03M13/03

摘要： Disclosed is an apparatus and method for operating a multi-level cell (MLC) flash memory circuit. Data is read from a memory block of a plurality of memory blocks in the MLC flash memory circuit, wherein each of the plurality of memory blocks can operate in one of at least three modes of operation comprising an MLC mode, a single-level cell (SLC) mode and a defective mode, and wherein the memory block is initially operating in the MLC mode. Error correction is performed on the read data to correct read errors in the read data. A determination is made if a number of bits corrected by the error correction exceeds a predetermined threshold value. If the number of bits corrected by the error correction exceeds the predetermined threshold value, the operating mode of the memory block is switched from the MLC mode to the SLC mode.

摘要翻译： 公开了一种用于操作多电平单元（MLC）闪速存储器电路的装置和方法。 从MLC闪速存储器电路中的多个存储器块的存储器块读取数据，其中多个存储器块中的每一个可以在至少三种操作模式中的一种操作，包括MLC模式，单级单元（ SLC）模式和缺陷模式，并且其中存储块最初在MLC模式下操作。 对读取的数据进行错误校正，以纠正读取数据中的读取错误。 如果通过纠错校正的位数超过预定阈值，则确定。 如果通过纠错校正的比特数超过预定阈值，则将存储块的操作模式从MLC模式切换到SLC模式。

公开(公告)号：US07650561B1

公开(公告)日：2010-01-19

申请号：US11484462

申请日：2006-07-11

申请人： Bengt A. Ulriksson ,  Richard D. Barndt

发明人： Bengt A. Ulriksson ,  Richard D. Barndt

IPC分类号： H03M13/03

CPC分类号： H03M13/2957 ,  H03M13/3707 ,  H03M13/3905 ,  H03M13/3966 ,  H03M13/3972

摘要： A MAP detector system operates in a parallel mode for on-the-fly operations and in a serial mode for error recovery operations. In the parallel mode, a plurality of Viterbi operators process a block of input sampled data in parallel. In the serial mode a selected forward Viterbi operator and two associated reverse Viterbi operators process the entire block of data, in order, to produce soft decision data.

摘要翻译： MAP检测器系统以并行模式操作，用于实时操作和串行模式用于错误恢复操作。 在并行模式中，多个维特比运算符并行地处理一组输入采样数据。 在串行模式下，选择的前向维特比运算符和两个相关的反向维特比运算符按顺序处理整个数据块，以产生软判决数据。

公开(公告)号：US06275350B1

公开(公告)日：2001-08-14

申请号：US09054648

申请日：1998-04-03

申请人： Richard D. Barndt

发明人： Richard D. Barndt

IPC分类号： G11B5584

CPC分类号： G11B5/5504

摘要： A multi-transducer magnetic head includes an array of transducer pairs positioned across at least a portion of a cross section of a magnetic tape path. Each transducer pair includes at least one write transducer and at least one read transducer. Within each transducer pair, a first centerline through the write transducer is generally parallel to a second centerline through the read transducer. Distances between the first and second centerlines within individual transducer pairs increase with distances of the transducer pairs from a head position reference point. In the preferred embodiment, the write transducers have a first pitch and the read transducers have a second pitch. However, the read transducers are biased toward the head position reference point, so that the pitch of the read transducers is smaller than the pitch of the write transducers. The method of determining the positions of the read and write transducers includes (1) dividing the sources of transducer-to-track alignment errors into biased and non-biased sources, (2) calculating preferred margins to compensate for the non-biased sources, and (3) laterally biasing the read transducers, the write transducers, or both to compensate for the biased sources.

摘要翻译： 多换能器磁头包括位于磁带路径的横截面的至少一部分上的换能器对的阵列。 每个换能器对包括至少一个写换能器和至少一个读换能器。 在每个换能器对内，通过写换能器的第一中心线通常通过读取换能器与第二中心线平行。 单个换能器对中的第一和第二中心线之间的距离随着换能器对与头部位置参考点的距离而增加。 在优选实施例中，写换能器具有第一间距，并且读换能器具有第二间距。 然而，读取换能器偏向头位置参考点，使得读换能器的间距小于写换能器的间距。 确定读取和写入换能器的位置的方法包括（1）将换能器到轨道对准误差源划分为偏置和非偏置源，（2）计算优选余量以补偿非偏置源， 和（3）横向偏置读取换能器，写入换能器或两者以补偿偏置源。