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1.发明授权公开(公告)号：US11956953B2
公开(公告)日：2024-04-09
申请号：US17934161
申请日：2022-09-21
发明人： Zhenyu Lu , Wenguang Shi , Guanping Wu , Feng Pan , Xianjin Wan , Baoyou Chen
摘要： Joint opening structures of 3D memory devices and fabricating method are provided. A joint opening structure comprises a first through hole penetrating a first stacked layer and a first insulating connection layer, a first channel structure at the bottom of the first through hole, a first functional layer on the sidewall of the first through hole, a second channel structure on the sidewall of the first functional layer, a third channel structure over the first through hole, a second stacked layer on the third channel structure, a second insulating connection layer on the second stacked layer, a second through hole penetrating the second stacked layer and the second insulating connection layer, a second functional layer disposed on the sidewall of the second through hole, a fourth channel structure on the sidewall of the second functional layer, and a fifth channel structure over the second through hole.
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2.发明授权公开(公告)号：US11482532B2
公开(公告)日：2022-10-25
申请号：US16951141
申请日：2020-11-18
发明人： Zhenyu Lu , Wenguang Shi , Guanping Wu , Feng Pan , Xianjin Wan , Baoyou Chen
IPC分类号： H01L27/00 , H01L27/11578 , H01L27/1157 , H01L27/11582 , H01L27/11565
摘要： Joint opening structures of 3D memory devices and fabricating method are provided. A joint opening structure comprises a first through hole penetrating a first stacked layer and a first insulating connection layer, a first channel structure at the bottom of the first through hole, a first functional layer on the sidewall of the first through hole, a second channel structure on the sidewall of the first functional layer, a third channel structure over the first through hole, a second stacked layer on the third channel structure, a second insulating connection layer on the second stacked layer, a second through hole penetrating the second stacked layer and the second insulating connection layer, a second functional layer disposed on the sidewall of the second through hole, a fourth channel structure on the sidewall of the second functional layer, and a fifth channel structure over the second through hole.
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公开(公告)号：US10790295B2
公开(公告)日：2020-09-29
申请号：US16046750
申请日：2018-07-26
发明人： Xiang Hui Zhao , Zui Xin Zeng , Jun Hu , Shi Zhang , Baoyou Chen
IPC分类号： H01L27/11582 , H01L27/11556 , H01L27/11573 , H01L21/768 , H01L23/522 , H01L23/528 , H01L27/11521 , H01L27/11529 , H01L27/11568 , H01L23/532
摘要： A method for forming a staircase structure of 3D memory, including: forming an alternating layer stack on a substrate, forming a plurality of staircase regions where each staircase region has a staircase structure having a first number (M) of steps in a first direction; forming a first mask stack to expose a plurality of the staircase regions; removing (M) of the layer stacks in the exposed staircase regions; forming a second mask stack over the alternating layer stack to expose at least an edge of each of the staircase regions in a second direction; and repetitively, sequentially, removing a portion of (2M) of layer stacks and trimming the second mask stack.
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公开(公告)号：US20230389323A1
公开(公告)日：2023-11-30
申请号：US18231749
申请日：2023-08-08
发明人： Zhenyu Lu , Wenguang Shi , Guanping Wu , Xianjin Wan , Baoyou Chen
IPC分类号： H10B43/50 , H10B43/10 , H10B43/27 , H10B43/40 , H01L23/522 , H01L23/535
CPC分类号： H10B43/50 , H10B43/10 , H10B43/27 , H10B43/40 , H01L23/5226 , H01L23/535 , H10B43/35
摘要： A three-dimensional (3D) memory device includes a staircase region including a first stack and a second stack, a barrier structure extending vertically through the first stack and laterally separating the first stack from the second stack, and a through array contact extending vertically through the first stack. The first stack includes first and second dielectric layers arranged alternately in a vertical direction. The second stack includes conductor layers and third dielectric layers arranged alternately in the vertical direction. The barrier structure includes an unclosed shape.
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5.发明申请公开(公告)号：US20230016627A1
公开(公告)日：2023-01-19
申请号：US17934161
申请日：2022-09-21
发明人： Zhenyu LU , Wenguang Shi , Guanping Wu , Feng Pan , Xianjin Wan , Baoyou Chen
IPC分类号： H01L27/11578 , H01L27/1157 , H01L27/11565 , H01L27/11582
摘要： Joint opening structures of 3D memory devices and fabricating method are provided. A joint opening structure comprises a first through hole penetrating a first stacked layer and a first insulating connection layer, a first channel structure at the bottom of the first through hole, a first functional layer on the sidewall of the first through hole, a second channel structure on the sidewall of the first functional layer, a third channel structure over the first through hole, a second stacked layer on the third channel structure, a second insulating connection layer on the second stacked layer, a second through hole penetrating the second stacked layer and the second insulating connection layer, a second functional layer disposed on the sidewall of the second through hole, a fourth channel structure on the sidewall of the second functional layer, and a fifth channel structure over the second through hole.
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6.发明授权公开(公告)号：US10886291B2
公开(公告)日：2021-01-05
申请号：US16046847
申请日：2018-07-26
发明人： Zhenyu Lu , Wenguang Shi , Guanping Wu , Feng Pan , Xianjin Wan , Baoyou Chen
IPC分类号： H01L21/00 , H01L27/11578 , H01L27/1157 , H01L27/11582 , H01L27/11565
摘要： Joint opening structures of 3D memory devices and fabricating method are provided. A joint opening structure comprises a first through hole penetrating a first stacked layer and a first insulating connection layer, a first channel structure at the bottom of the first through hole, a first functional layer on the sidewall of the first through hole, a second channel structure on the sidewall of the first functional layer, a third channel structure over the first through hole, a second stacked layer on the third channel structure, a second insulating connection layer on the second stacked layer, a second through hole penetrating the second stacked layer and the second insulating connection layer, a second functional layer disposed on the sidewall of the second through hole, a fourth channel structure on the sidewall of the second functional layer, and a fifth channel structure over the second through hole.
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公开(公告)号：US11997851B2
公开(公告)日：2024-05-28
申请号：US17004846
申请日：2020-08-27
发明人： Xiang Hui Zhao , Zui Xin Zeng , Jun Hu , Shi Zhang , Baoyou Chen
IPC分类号： H10B41/50 , H01L21/768 , H01L23/522 , H01L23/528 , H10B41/27 , H10B41/30 , H10B41/41 , H10B43/27 , H10B43/30 , H10B43/40 , H10B43/50 , H01L23/532
CPC分类号： H10B43/40 , H01L21/76816 , H01L21/76877 , H01L23/5226 , H01L23/5283 , H10B41/27 , H10B41/30 , H10B41/41 , H10B41/50 , H10B43/27 , H10B43/30 , H10B43/50 , H01L23/53209 , H01L23/53214 , H01L23/53242 , H01L23/53257 , H01L23/53271 , H01L23/5329
摘要： A method for forming a staircase structure of 3D memory, including: forming an alternating layer stack on a substrate, forming a plurality of staircase regions where each staircase region has a staircase structure having a first number (M) of steps in a first direction; forming a first mask stack to expose a plurality of the staircase regions; removing (M) of the layer stacks in the exposed staircase regions; forming a second mask stack over the alternating layer stack to expose at least an edge of each of the staircase regions in a second direction; and repetitively, sequentially, removing a portion of (2M) of layer stacks and trimming the second mask stack.
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公开(公告)号：US10804283B2
公开(公告)日：2020-10-13
申请号：US16046475
申请日：2018-07-26
发明人： Jia He , Haihui Huang , Fandong Liu , Yaohua Yang , Peizhen Hong , Zhiliang Xia , Zongliang Huo , Yaobin Feng , Baoyou Chen , Qingchen Cao
IPC分类号： H01L27/1157 , H01L27/11578 , H01L29/66 , H01L29/792 , H01L21/28 , H01L27/11582
摘要： Embodiments of semiconductor devices and methods for forming the semiconductor devices are disclosed. In an example, a method for forming device openings includes forming a material layer over a first region and a second region of a substrate, the first region being adjacent to the second region, forming a mask layer over the material layer, the mask layer covering the first region and the second region, and forming a patterning layer over the mask layer. The patterning layer covers the first region and the second region and including openings corresponding to the first region. The plurality of openings includes a first opening adjacent to a boundary between the first region and the second region and a second opening further away from the boundary. Along a plane parallel to a top surface of the substrate, a size of the first opening is greater than a size of the second opening.
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公开(公告)号：US20190013327A1
公开(公告)日：2019-01-10
申请号：US16046475
申请日：2018-07-26
发明人： Jia He , Haihui Huang , Fandong Liu , Yaohua Yang , Peizhen Hong , Zhiliang Xia , Zongliang Huo , Yaobin Feng , Baoyou Chen , Qingchen Cao
IPC分类号： H01L27/11578 , H01L27/1157 , H01L29/792 , H01L29/66 , H01L21/28
摘要： Embodiments of semiconductor devices and methods for forming the semiconductor devices are disclosed. In an example, a method for forming device openings includes forming a material layer over a first region and a second region of a substrate, the first region being adjacent to the second region, forming a mask layer over the material layer, the mask layer covering the first region and the second region, and forming a patterning layer over the mask layer. The patterning layer covers the first region and the second region and including openings corresponding to the first region. The plurality of openings includes a first opening adjacent to a boundary between the first region and the second region and a second opening further away from the boundary. Along a plane parallel to a top surface of the substrate, a size of the first opening is greater than a size of the second opening.
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公开(公告)号：US20240107757A1
公开(公告)日：2024-03-28
申请号：US18534480
申请日：2023-12-08
发明人： Jia He , Haihui Huang , Fandong Liu , Yaohua Yang , Peizhen Hong , Zhiliang Xia , Zongliang Huo , Yaobin Feng , Baoyou Chen , Qingchen Cao
CPC分类号： H10B43/20 , H01L29/40117 , H01L29/66833 , H01L29/792 , H10B43/27 , H10B43/35
摘要： Embodiments of semiconductor devices and methods for forming the semiconductor devices are disclosed. In an example, a method for forming device openings includes forming a material layer over a first region and a second region of a substrate, the first region being adjacent to the second region, forming a mask layer over the material layer, the mask layer covering the first region and the second region, and forming a patterning layer over the mask layer. The patterning layer covers the first region and the second region and including openings corresponding to the first region. The plurality of openings includes a first opening adjacent to a boundary between the first region and the second region and a second opening further away from the boundary. Along a plane parallel to a top surface of the substrate, a size of the first opening is greater than a size of the second opening.
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