公开(公告)号：US07605065B2

公开(公告)日：2009-10-20

申请号：US11839704

申请日：2007-08-16

申请人： Moon Gyu Jang ,  Yark Yeon Kim ,  Jae Heon Shin ,  Seong Jae Lee

发明人： Moon Gyu Jang ,  Yark Yeon Kim ,  Jae Heon Shin ,  Seong Jae Lee

IPC分类号： H01L21/28 ,  H01L21/44

CPC分类号： H01L29/7613 ,  B82Y10/00 ,  H01L29/872

摘要： Provided are a Schottky barrier tunnel single electron transistor and a method of manufacturing the same that use a Schottky barrier formed between metal and semiconductor by replacing a source and a drain with silicide as a reactant of silicon and metal, instead of a conventional method of manufacturing a single electron transistor (SET) that includes source and drain regions by implanting dopants such that an artificial quantum dot is formed in a channel region. As a result, it does not require a conventional PADOX process to form a quantum dot for a single electron transistor (SET), height and width of a tunneling barrier can be artificially adjusted by using silicide materials that have various Schottky junction barriers, and it is possible to improve current driving capability of the single electron transistor (SET).

摘要翻译： 提供了一种肖特基势垒隧道单电子晶体管及其制造方法，其替代传统的制造方法，而是用硅化物替代源极和漏极作为硅和金属的反应物，从而形成金属和半导体之间形成的肖特基势垒 单电子晶体管（SET），其通过注入掺杂剂而包括源极和漏极区域，使得在沟道区域中形成人造量子点。 结果，不需要传统的PADOX工艺来形成单电子晶体管（SET）的量子点，隧道势垒的高度和宽度可以通过使用具有各种肖特基结屏障的硅化物材料进行人工调整，而且 可以提高单电子晶体管（SET）的电流驱动能力。

公开(公告)号：US07566642B2

公开(公告)日：2009-07-28

申请号：US11188076

申请日：2005-07-22

申请人： Yark Yeon Kim ,  Moon Gyu Jang ,  Jae Heon Shin ,  Seong Jae Lee

发明人： Yark Yeon Kim ,  Moon Gyu Jang ,  Jae Heon Shin ,  Seong Jae Lee

IPC分类号： H01L21/44

CPC分类号： H01L29/665 ,  H01L21/2252 ,  H01L21/2254 ,  H01L21/28518 ,  H01L21/28537 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7839

摘要： An n-type SBTT and a manufacturing method thereof are provided. The SBTT includes a silicon layer, a gate, a double layer that has a rare-earth metal silicide layer and a transition metal silicide layer. The silicon layer has a channel region. The gate is formed in an overlapping manner on the channel region and has a gate dielectric layer on its interface with respect to the silicon layer. The double layer is formed as a source/drain that has the channel region interposed on the silicon layer.

摘要翻译： 提供了n型SBTT及其制造方法。 SBTT包括硅层，栅极，具有稀土金属硅化物层和过渡金属硅化物层的双层。 硅层具有沟道区。 栅极以重叠的方式形成在沟道区上，并且在其相对于硅层的界面上具有栅极介电层。 双层形成为具有介于硅层之间的沟道区的源极/漏极。

公开(公告)号：US20090250756A1

公开(公告)日：2009-10-08

申请号：US12485777

申请日：2009-06-16

申请人： Yark Yeon Kim ,  Moon Gyu Jang ,  Jae Heon Shin ,  Seong Jae Lee

发明人： Yark Yeon Kim ,  Moon Gyu Jang ,  Jae Heon Shin ,  Seong Jae Lee

IPC分类号： H01L27/12

CPC分类号： H01L29/665 ,  H01L21/2252 ,  H01L21/2254 ,  H01L21/28518 ,  H01L21/28537 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7839

摘要： An n-type SBTT and a manufacturing method thereof are provided. The SBTT includes a silicon layer, a gate, a double layer that has a rare-earth metal silicide layer and a transition metal silicide layer. The silicon layer has a channel region. The gate is formed in an overlapping manner on the channel region and has a gate dielectric layer on its interface with respect to the silicon layer. The double layer is formed as a source/drain that has the channel region interposed on the silicon layer.

摘要翻译： 提供了n型SBTT及其制造方法。 SBTT包括硅层，栅极，具有稀土金属硅化物层和过渡金属硅化物层的双层。 硅层具有沟道区。 栅极以重叠的方式形成在沟道区上，并且在其相对于硅层的界面上具有栅极介电层。 双层形成为具有介于硅层之间的沟道区的源极/漏极。

公开(公告)号：US07312510B2

公开(公告)日：2007-12-25

申请号：US11187654

申请日：2005-07-22

申请人： Jae Heon Shin ,  Moon Gyu Jang ,  Yark Yeon Kim ,  Seong Jae Lee

发明人： Jae Heon Shin ,  Moon Gyu Jang ,  Yark Yeon Kim ,  Seong Jae Lee

IPC分类号： H01L29/47

CPC分类号： H01L29/7839 ,  G11C11/56

摘要： A device using an ambipolar transport of an SB-MOSFET and a method for operating the same are provided. The SB-MOSFET includes: a silicon channel region; a source and a drain contacted on both sides of the channel region and formed of material including metal layer; and a gate formed on the channel region, with a gate dielectric layer interposed therebetween. Positive (+), 0 or negative (−) gate voltage is selectively applied to the gate, the channel becomes off-state when the gate voltage between a negative threshold voltage and a positive threshold voltage is applied, and the channel becomes a first on-state and a second on-state when the gate voltage is lower than the negative threshold voltage or higher than the positive threshold voltage. Accordingly, it is possible to implement three current states, that is, hole current, electron current, and no current. The SB-MOSFET can be applied to a multi-bit memory and/or multi-bit logic device.

摘要翻译： 提供了使用SB-MOSFET的双极运输的装置及其操作方法。 SB-MOSFET包括：硅沟道区; 源极和漏极在沟道区域的两侧接触并由包括金属层的材料形成; 以及形成在沟道区上的栅极，介于其间的栅介质层。 正极（+），0或负（ - ）栅极电压选择性地施加到栅极，当施加负阈值电压和正阈值电压之间的栅极电压时，通道变为截止状态，并且通道变为第一个 当门电压低于负阈值电压或高于正阈值电压时，状态和第二导通状态。 因此，可以实现三种电流状态，即空穴电流，电子电流，无电流。 SB-MOSFET可以应用于多位存储器和/或多位逻辑器件。

公开(公告)号：US07268407B2

公开(公告)日：2007-09-11

申请号：US11196180

申请日：2005-08-03

申请人： Moon Gyu Jang ,  Yark Yeon Kim ,  Jae Heon Shin ,  Seong Jae Lee

发明人： Moon Gyu Jang ,  Yark Yeon Kim ,  Jae Heon Shin ,  Seong Jae Lee

IPC分类号： H01L31/07

CPC分类号： H01L29/7613 ,  B82Y10/00 ,  H01L29/872

摘要： Provided are a Schottky barrier tunnel single electron transistor and a method of manufacturing the same that use a Schottky barrier formed between metal and semiconductor by replacing a source and a drain with silicide as a reactant of silicon and metal, instead of a conventional method of manufacturing a single electron transistor (SET) that includes source and drain regions by implanting dopants such that an artificial quantum dot is formed in a channel region. As a result, it does not require a conventional PADOX process to form a quantum dot for a single electron transistor (SET), height and width of a tunneling barrier can be artificially adjusted by using silicide materials that have various Schottky junction barriers, and it is possible to improve current driving capability of the single electron transistor (SET).

摘要翻译： 提供了一种肖特基势垒隧道单电子晶体管及其制造方法，其替代传统的制造方法，而是用硅化物替代源极和漏极作为硅和金属的反应物，从而形成金属和半导体之间形成的肖特基势垒 单电子晶体管（SET），其通过注入掺杂剂而包括源极和漏极区域，使得在沟道区域中形成人造量子点。 结果，不需要传统的PADOX工艺来形成单电子晶体管（SET）的量子点，隧道势垒的高度和宽度可以通过使用具有各种肖特基结屏障的硅化物材料进行人工调整，而且 可以提高单电子晶体管（SET）的电流驱动能力。

公开(公告)号：US07981735B2

公开(公告)日：2011-07-19

申请号：US12434779

申请日：2009-05-04

申请人： Yark Yeon Kim ,  Seong Jae Lee ,  Moon Gyu Jang ,  Chel Jong Choi ,  Myung Sim Jun ,  Byoung Chul Park

发明人： Yark Yeon Kim ,  Seong Jae Lee ,  Moon Gyu Jang ,  Chel Jong Choi ,  Myung Sim Jun ,  Byoung Chul Park

IPC分类号： H01L21/336

CPC分类号： H01L29/47 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/7839

摘要： Provided are a Schottky barrier tunnel transistor and a method of manufacturing the same that are capable of minimizing leakage current caused by damage to a gate sidewall of the Schottky barrier tunnel transistor using a Schottky tunnel barrier naturally formed at a semiconductor-metal junction as a tunnel barrier. The method includes the steps of: forming a semiconductor channel layer on an insulating substrate; forming a dummy gate on the semiconductor channel layer; forming a source and a drain at both sides of the dummy gate on the insulating substrate; removing the dummy gate; forming an insulating layer on a sidewall from which the dummy gate is removed; and forming an actual gate in a space from which the dummy gate is removed. In manufacturing the Schottky barrier tunnel transistor using the dummy gate, it is possible to form a high-k dielectric gate insulating layer and a metal gate, and stable characteristics in silicidation of the metal layer having very strong reactivity can be obtained.

摘要翻译： 提供了一种肖特基势垒隧道晶体管及其制造方法，该晶体管能够使用在半导体 - 金属结上自然形成的肖特基隧道势垒作为隧道来最小化对肖特基势垒隧道晶体管的栅极侧壁的损坏所造成的漏电流 屏障。 该方法包括以下步骤：在绝缘基板上形成半导体沟道层; 在半导体沟道层上形成虚拟栅极; 在绝缘基板上的虚拟栅极的两侧形成源极和漏极; 去除虚拟门; 在去除所述伪栅极的侧壁上形成绝缘层; 并且在从其中去除虚拟栅极的空间中形成实际栅极。 在使用伪栅极制造肖特基势垒隧道晶体管时，可以形成高k电介质栅极绝缘层和金属栅极，并且可以获得具有非常强反应性的金属层的硅化物的稳定特性。

公开(公告)号：US07545000B2

公开(公告)日：2009-06-09

申请号：US11485837

申请日：2006-07-13

申请人： Yark Yeon Kim ,  Seong Jae Lee ,  Moon Gyu Jang ,  Chel Jong Choi ,  Myung Sim Jun ,  Byoung Chul Park

发明人： Yark Yeon Kim ,  Seong Jae Lee ,  Moon Gyu Jang ,  Chel Jong Choi ,  Myung Sim Jun ,  Byoung Chul Park

IPC分类号： H01L27/01

CPC分类号： H01L29/47 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/7839

摘要： Provided are a Schottky barrier tunnel transistor and a method of manufacturing the same that are capable of minimizing leakage current caused by damage to a gate sidewall of the Schottky barrier tunnel transistor using a Schottky tunnel barrier naturally formed at a semiconductor-metal junction as a tunnel barrier. The method includes the steps of: forming a semiconductor channel layer on an insulating substrate; forming a dummy gate on the semiconductor channel layer; forming a source and a drain at both sides of the dummy gate on the insulating substrate; removing the dummy gate; forming an insulating layer on a sidewall from which the dummy gate is removed; and forming an actual gate in a space from which the dummy gate is removed. In manufacturing the Schottky barrier tunnel transistor using the dummy gate, it is possible to form a high-k dielectric gate insulating layer and a metal gate, and stable characteristics in silicidation of the metal layer having very strong reactivity can be obtained.

摘要翻译： 提供了一种肖特基势垒隧道晶体管及其制造方法，该晶体管能够使用在半导体 - 金属结上自然形成的肖特基隧道势垒作为隧道，将肖特基势垒隧道晶体管的栅极侧壁损坏所造成的漏电流减到最小 屏障。 该方法包括以下步骤：在绝缘基板上形成半导体沟道层; 在半导体沟道层上形成虚拟栅极; 在绝缘基板上的虚拟栅极的两侧形成源极和漏极; 去除虚拟门; 在去除所述伪栅极的侧壁上形成绝缘层; 并且在从其中去除虚拟栅极的空间中形成实际栅极。 在使用伪栅极制造肖特基势垒隧道晶体管时，可以形成高k电介质栅极绝缘层和金属栅极，并且可以获得具有非常强反应性的金属层的硅化物的稳定特性。

公开(公告)号：US07005356B2

公开(公告)日：2006-02-28

申请号：US10746493

申请日：2003-12-23

申请人： Woo Seok Cheong ,  Seong Jae Lee ,  Moon Gyu Jang

发明人： Woo Seok Cheong ,  Seong Jae Lee ,  Moon Gyu Jang

IPC分类号： H01L21/28

CPC分类号： H01L21/28114 ,  H01L21/28123 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/66643 ,  H01L29/7839 ,  H01L29/78654

摘要： A schottky barrier transistor and a method of manufacturing the same are provided. The method includes forming a gate insulating layer and a gate on a substrate, forming a spacer on a sidewall of the gate, and growing a polycrystalline silicon layer and a monocrystalline silicon layer on the gate and the substrate, respectively, using a selective silicon growth. A metal is deposited on the polycrystalline silicon layer and the monocrystalline silicon layer. Then, the metal reacts with silicon of the polycrystalline silicon layer and the monocyrstalline silicon layer to form a self-aligned metal silicide layer. Therefore, selective wet etching for removing an unreacted metal after silicidation can be omitted. Furthermore, etching damage caused during the formation of the spacer can be decreased during the growth of the monocrystalline silicon layer, thereby improving the electrical characteristics of devices.

摘要翻译： 提供肖特基势垒晶体管及其制造方法。 该方法包括在衬底上形成栅极绝缘层和栅极，在栅极的侧壁上形成间隔物，并使用选择性硅生长分别在栅极和衬底上生长多晶硅层和单晶硅层 。 金属沉积在多晶硅层和单晶硅层上。 然后，金属与多晶硅层和单晶硅层的硅反应形成自对准的金属硅化物层。 因此，可以省略用于除去硅化后的未反应金属的选择性湿法蚀刻。 此外，在单晶硅层的生长期间，可以减少在间隔物形成期间引起的蚀刻损伤，从而提高器件的电气特性。

公开(公告)号：US06797629B2

公开(公告)日：2004-09-28

申请号：US10185104

申请日：2002-06-27

申请人： Moon Gyu Jang ,  Won Ju Cho ,  Seong Jae Lee ,  Kyoung Wan Park

发明人： Moon Gyu Jang ,  Won Ju Cho ,  Seong Jae Lee ,  Kyoung Wan Park

IPC分类号： H01L21302

CPC分类号： H01L29/78648 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78654

摘要： The present invention relates to a method of manufacturing a nano transistor. The present invention manufactures the nano transistor without changing a conventional method of forming the nano transistor formed on a SOI substrate. Further, the present invention includes forming a N well and a P well at giving regions of an underlying silicon substrate so that a given voltage can be individually applied to a NMOS transistor and a PMOS transistor. Therefore, the present invention can control the threshold voltage to prevent an increase of the leakage current.

摘要翻译： 本发明涉及纳米晶体管的制造方法。 本发明制造纳米晶体管而不改变形成在SOI衬底上的纳米晶体管的常规方法。 此外，本发明包括在给定下面的硅衬底的区域上形成N阱和P阱，使得可以将给定的电压单独地施加到NMOS晶体管和PMOS晶体管。 因此，本发明可以控制阈值电压以防止漏电流的增加。

公开(公告)号：US20070072336A1

公开(公告)日：2007-03-29

申请号：US11447820

申请日：2006-06-06

申请人： Han Young Yu ,  In Bok Baek ,  Chang Geun Ahn ,  Ki Ju Im ,  Jong Heon Yang ,  Ung Hwan Pi ,  Min Ki Ryu ,  Chan Woo Park ,  Sung Yool Choi ,  Seong Jae Lee

发明人： Han Young Yu ,  In Bok Baek ,  Chang Geun Ahn ,  Ki Ju Im ,  Jong Heon Yang ,  Ung Hwan Pi ,  Min Ki Ryu ,  Chan Woo Park ,  Sung Yool Choi ,  Seong Jae Lee

IPC分类号： H01L51/40 ,  C25D5/18

CPC分类号： H01L51/105 ,  B82Y10/00 ,  H01L51/0023 ,  H01L51/0595

摘要： Provided is a method of manufacturing a nano size-gap electrode device. The method includes the steps of: disposing a floated nano structure on a semiconductor layer; forming a mask layer having at least one opening pattern to intersect the nano structure; and depositing a metal on the semiconductor layer exposed through the opening pattern to form an electrode, such that a nano size-gap is provided under the nano structure by the nano structure.

摘要翻译： 提供一种制造纳米尺寸间隙电极器件的方法。 该方法包括以下步骤：在半导体层上设置浮动的纳米结构; 形成具有至少一个开口图案以与纳米结构相交的掩模层; 以及在通过所述开口图案暴露的所述半导体层上沉积金属以形成电极，使得通过所述纳米结构在所述纳米结构下方提供纳米尺寸间隙。