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    PITCH SHIFT DEVICE AND PROCESS
    2.
    发明申请
    PITCH SHIFT DEVICE AND PROCESS 有权
    PITCH SHIFT设备和过程

    公开(公告)号：US20120137856A1

    公开(公告)日：2012-06-07

    申请号：US13301635

    申请日：2011-11-21

    申请人： Yasuhiro Fukuda ,  Shoichi Ikeda

    发明人： Yasuhiro Fukuda ,  Shoichi Ikeda

    IPC分类号： G10H7/00

    CPC分类号： G10H1/20 ,  G10H3/125 ,  G10H2210/261 ,  G10H2250/035

    摘要： A pitch shift device provides pitch-shifted sounds based on performance sounds generated by an electronic string musical instrument. The pitch shift device has a device that detects vibrato. When vibrato is detected, an interpolation device of a pitch shift control device performs a control of interpolating for a pitch shift change in the musical sound signal accompanying a change in pitch shift information stored in a pitch information storage device and read out by a pitch shift readout device from a group of pitch shift information. Therefore, unnatural pitch changes in pitch-shifted sound can be suppressed.

    摘要翻译： 音调移位装置基于由电子乐器产生的演奏声音提供音调偏移的声音。 音高移位装置具有检测颤音的装置。 当检测到颤音时，音调移位控制装置的内插装置对音乐信号中随音调信息存储装置中存储的音调偏移信息的变化进行音调偏移改变进行内插控制，并通过音调偏移读出 读出装置从一组音调移位信息。 因此，可以抑制音调移动声音的非自然音高变化。

    SEMICONDUCTOR DEVICE WITH ESD PROTECTION FUNCTION AND ESD PROTECTION CIRCUIT
    3.
    发明申请
    SEMICONDUCTOR DEVICE WITH ESD PROTECTION FUNCTION AND ESD PROTECTION CIRCUIT 失效
    具有ESD保护功能和ESD保护电路的半导体器件

    公开(公告)号：US20100134938A1

    公开(公告)日：2010-06-03

    申请号：US12688080

    申请日：2010-01-15

    申请人： Yasuhiro Fukuda

    发明人： Yasuhiro Fukuda

    IPC分类号： H02H9/04

    CPC分类号： H01L27/0255 ,  H01L21/84 ,  H01L27/0266 ,  H01L27/1203

    摘要： A semiconductor device with an ESD protection function has an SOI substrate, first to fourth diffusion layers, and a gate. The SOI substrate has a semiconductor layer on an insulation layer. The first diffusion layer is of a first conductivity type and is formed on the semiconductor layer. The second diffusion layer is of the first conductivity type and is formed on the semiconductor layer. The third diffusion layer is of a second conductivity type and is formed on the semiconductor layer so as to be adjacent to the first and second diffusion layers. The fourth diffusion layer is of the second conductivity type and is formed on the semiconductor layer so as to be adjacent to the first diffusion layer and electrically connected to the second diffusion layer. The gate is formed over the third diffusion layer.

    摘要翻译： 具有ESD保护功能的半导体器件具有SOI衬底，第一至第四扩散层和栅极。 SOI衬底在绝缘层上具有半导体层。 第一扩散层是第一导电类型并形成在半导体层上。 第二扩散层是第一导电类型，并形成在半导体层上。 第三扩散层是第二导电类型，并且形成在半导体层上以便与第一和第二扩散层相邻。 第四扩散层是第二导电类型，并且形成在半导体层上以与第一扩散层相邻并且电连接到第二扩散层。 栅极形成在第三扩散层上。

    Driving circuit
    4.
    发明授权
    Driving circuit 有权
    驱动电路

    公开(公告)号：US06919870B2

    公开(公告)日：2005-07-19

    申请号：US09887594

    申请日：2001-06-22

    申请人： Yasuhiro Fukuda

    发明人： Yasuhiro Fukuda

    IPC分类号： G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  G11C19/00 ,  H03F1/02 ,  H03F3/34 ,  H03F3/72

    CPC分类号： G11C19/00 ,  G09G3/3614 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2310/0291 ,  G09G2310/0294 ,  G09G2310/0297 ,  G09G2320/02 ,  G09G2330/021

    摘要： The objective of this invention is to compensate or avoid the influence of offset in an easy and efficient manner, to correctly match the voltage of the output signal with the voltage of the input signal, that is, the target value, and to significantly reduce the current consumption. When voltage follower 32L supplies bias voltage VBn to each of constant current source circuits 58L, 60L, it acts as a source-type voltage follower. However, when the bias voltage applied to each of constant current source circuits 58L, 60L is changed from VBn to Vss of the power supply voltage level, each of constant current source circuits 58L, 60L is turned off, and no current flows through them. When the constant current source circuit 58 is turned off in differential input part 44L, the potential at the output terminal (node) NL rises almost to the level of the power supply voltage Vdd. In this way, the driving transistor 62L is also turned off in output part 46L.

    摘要翻译： 本发明的目的是以容易和有效的方式补偿或避免偏移的影响，以将输出信号的电压与输入信号的电压，即目标值正确地匹配，并且显着地减少 目前的消费。 当电压跟随器32L向每个恒流源电路58L，60L提供偏置电压VBn时，其作为源极型电压跟随器。 然而，当施加到恒定电流源电路58L，60L中的每一个的偏置电压从电源电压电平的VBn变为Vss时，恒流源电路58L，60L中的每一个都断开，并且没有电流 流过他们。 当差动输入部分44L中的恒流源电路58断开时，输出端（节点）NL处的电位几乎上升到电源电压Vdd的电平。 以这种方式，驱动晶体管62L也在输出部分46L中截止。

    Method of and apparatus for testing semiconductor device for electrostatic discharge damage
    5.
    发明授权
    Method of and apparatus for testing semiconductor device for electrostatic discharge damage 失效
    用于测试用于静电放电损坏的半导体器件的方法和装置

    公开(公告)号：US4823088A

    公开(公告)日：1989-04-18

    申请号：US42424

    申请日：1987-04-24

    申请人： Yasuhiro Fukuda

    发明人： Yasuhiro Fukuda

    IPC分类号： G01R31/26 ,  G01R31/12 ,  G01R31/30 ,  G01R31/3161 ,  G01N27/60

    CPC分类号： G01R31/3161 ,  G01R31/129

    摘要： A method of testing the susceptibility of a semiconductor device having a dielectric package to withstand electrostatic charges charged on the dielectric package, comprising the steps of: connecting a switch in between input/output terminals of the semiconductor device and a reference potential source, applying a prescribed potential to the surface of the dielectric package to charge the surface with electric charges while the switch is in an open state, applying a prescribed potential to a terminal of the semiconductor device via a resistor, and discharging the charges to the reference potential source by closing the switch.

    Semiconductor device having fuse and protection circuit
    7.
    发明授权
    Semiconductor device having fuse and protection circuit 有权
    具有保险丝和保护电路的半导体器件

    公开(公告)号：US07816761B2

    公开(公告)日：2010-10-19

    申请号：US11082922

    申请日：2005-03-18

    申请人： Noboru Egawa ,  Yasuhiro Fukuda

    发明人： Noboru Egawa ,  Yasuhiro Fukuda

    IPC分类号： H01L23/62

    CPC分类号： H01L23/5258 ,  H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device having a semiconductor substrate, an insulating layer, a fuse, a diffusion layer and a resistor. The semiconductor substrate has a first conductivity type. The insulating layer is selectively formed on the surface of the semiconductor substrate. The fuse is formed on the insulating layer. The diffusion layer has a second conductivity type. The diffusion layer is formed on the surface of the semiconductor substrate and electrically connected to the fuse. The first resistor is electrically connected to the fuse.

    摘要翻译： 具有半导体衬底，绝缘层，熔丝，扩散层和电阻器的半导体器件。 半导体衬底具有第一导电类型。 绝缘层选择性地形成在半导体衬底的表面上。 保险丝形成在绝缘层上。 扩散层具有第二导电类型。 扩散层形成在半导体衬底的表面上并与熔丝电连接。 第一个电阻器与保险丝电连接。

    Electro-static discharge protection circuit and semiconductor device having the same
    8.
    发明授权
    Electro-static discharge protection circuit and semiconductor device having the same 有权
    静电放电保护电路和具有相同的半导体器件

    公开(公告)号：US07498615B2

    公开(公告)日：2009-03-03

    申请号：US11276403

    申请日：2006-02-28

    申请人： Toshikazu Kuroda ,  Hirokazu Hayashi ,  Yasuhiro Fukuda

    发明人： Toshikazu Kuroda ,  Hirokazu Hayashi ,  Yasuhiro Fukuda

    IPC分类号： H01L29/74

    CPC分类号： H01L27/0262

    摘要： An electro-static discharge protection circuit includes a thyristor mode ensuring circuit and a thyristor rectifier circuit. The thyristor mode ensuring circuit includes a capacitive element connected between a higher potential line and a lower potential line, and ensures a constant and sufficient capacity independently of the number of input/output signal bits, even when the number of input/output signal bits is a theoretical minimum, i.e. 1, so that a surge current induced by electro-static discharge (ESD) applied to an output pad is injected into the first capacitive element to charge it. Thus, by means of the current caused by the surge current, the thyristor rectifier circuit is triggered into a thyristor mode, which allows the surge current to flow to the lower potential line through the thyristor rectifier circuit, protecting circuitry against the surge current.

    摘要翻译： 一种静电放电保护电路包括晶闸管模式保护电路和晶闸管整流电路。 晶闸管模式确保电路包括连接在较高电位线和下电位线之间的电容元件，并且即使当输入/输出信号位的数量为 理论最小值，即1，使得由施加到输出焊盘的静电放电（ESD）引起的浪涌电流被注入到第一电容元件中以对其充电。 因此，通过由浪涌电流引起的电流，晶闸管整流电路被触发成晶闸管模式，这允许浪涌电流通过晶闸管整流电路流向下电位线，保护电路免受浪涌电流的影响。

    SEMICONDUCTOR DEVICE WITH ESD PROTECTION FUNCTION AND ESD PROTECTION CIRCUIT
    9.
    发明申请
    SEMICONDUCTOR DEVICE WITH ESD PROTECTION FUNCTION AND ESD PROTECTION CIRCUIT 有权
    具有ESD保护功能和ESD保护电路的半导体器件

    公开(公告)号：US20060114628A1

    公开(公告)日：2006-06-01

    申请号：US11164205

    申请日：2005-11-14

    申请人： Yasuhiro Fukuda

    发明人： Yasuhiro Fukuda

    IPC分类号： H02H9/00

    CPC分类号： H01L27/0255 ,  H01L21/84 ,  H01L27/0266 ,  H01L27/1203

    摘要： A semiconductor device with an ESD protection function has an SOI substrate, first to fourth diffusion layers, and a gate. The SOI substrate has a semiconductor layer on an insulation layer. The first diffusion layer is of a first conductivity type and is formed on the semiconductor layer. The second diffusion layer is of the first conductivity type and is formed on the semiconductor layer. The third diffusion layer is of a second conductivity type and is formed on the semiconductor layer so as to be adjacent to the first and second diffusion layers. The fourth diffusion layer is of the second conductivity type and is formed on the semiconductor layer so as to be adjacent to the first diffusion layer and electrically connected to the second diffusion layer. The gate is formed over the third diffusion layer.

    摘要翻译： 具有ESD保护功能的半导体器件具有SOI衬底，第一至第四扩散层和栅极。 SOI衬底在绝缘层上具有半导体层。 第一扩散层是第一导电类型并形成在半导体层上。 第二扩散层是第一导电类型，并形成在半导体层上。 第三扩散层是第二导电类型，并且形成在半导体层上以便与第一和第二扩散层相邻。 第四扩散层是第二导电类型，并且形成在半导体层上以与第一扩散层相邻并且电连接到第二扩散层。 栅极形成在第三扩散层上。

    Deflection correction circuit for narrowing a pull-in range of a VCO to reduce frequency variations in a horizontal synchronizing signal
    10.
    发明授权
    Deflection correction circuit for narrowing a pull-in range of a VCO to reduce frequency variations in a horizontal synchronizing signal 失效
    用于缩小VCO的拉入范围以减小水平同步信号中的频率变化的偏转校正电路

    公开(公告)号：US06486857B1

    公开(公告)日：2002-11-26

    申请号：US09503177

    申请日：2000-02-14

    申请人： Takafumi Esaki ,  Yoshiyuki Uto ,  Hiroshi Furukawa ,  Yasuhiro Fukuda

    发明人： Takafumi Esaki ,  Yoshiyuki Uto ,  Hiroshi Furukawa ,  Yasuhiro Fukuda

    IPC分类号： G09G108

    CPC分类号： H03L7/197 ,  G09G1/04 ,  G09G5/18 ,  H03L7/18

    摘要： There is disclosed a phase-locked loop (PLL) circuit for use in an improved deflection correction circuit for a larger and flat display device. The PLL circuit has a phase comparator circuit, a filter, and a voltage-controlled oscillator (VCO) connected in series in this order. The output signal from the VCO is fed back to the phase comparator circuit. The PLL circuit further includes a period-detecting circuit for detecting the period of an externally applied signal and a frequency divider circuit. This frequency divider circuit divides the frequency of the output signal from the VCO according to the period detected by the period-detecting circuit and feeds the resulting signal back to the VCO.

    摘要翻译： 公开了一种用于更大和平坦的显示装置的改进的偏转校正电路中的锁相环（PLL）电路。 PLL电路具有按顺序串联连接的相位比较器电路，滤波器和压控振荡器（VCO）。 来自VCO的输出信号被反馈到相位比较器电路。 PLL电路还包括用于检测外部施加的信号的周期的周期检测电路和分频器电路。 该分频器电路根据由周期检测电路检测到的周期来分频来自VCO的输出信号的频率，并将所得到的信号反馈给VCO。