公开(公告)号：US07935597B2

公开(公告)日：2011-05-03

申请号：US12912609

申请日：2010-10-26

申请人： Yasuhiro Shimamoto ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shinichiro Kimura

发明人： Yasuhiro Shimamoto ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shinichiro Kimura

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  G11C16/0425 ,  H01L21/28282 ,  H01L21/31155 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/66833

摘要： Performance and reliability of a semiconductor device including a non-volatile memory are improved. A memory cell of the non-volatile memory includes, over an upper portion of a semiconductor substrate, a select gate electrode formed via a first dielectric film and a memory gate electrode formed via a second dielectric film formed of an ONO multilayered film having a charge storing function. The first dielectric film functions as a gate dielectric film, and includes a third dielectric film made of silicon oxide or silicon oxynitride and a metal-element-containing layer made of a metal oxide or a metal silicate formed between the select gate electrode and the third dielectric film. A semiconductor region positioned under the memory gate electrode and the second dielectric film has a charge density of impurities lower than that of a semiconductor region positioned under the select gate electrode and the first dielectric film.

摘要翻译： 提高了包括非易失性存储器的半导体器件的性能和可靠性。 非易失性存储器的存储单元包括在半导体衬底的上部上的经由第一电介质膜形成的选择栅电极和通过由具有电荷的ONO多层膜形成的第二电介质膜形成的存储栅电极 存储功能。 第一电介质膜用作栅极电介质膜，并且包括由氧化硅或氮氧化硅制成的第三电介质膜和由选择栅电极和第三电极之间形成的金属氧化物或金属硅酸盐构成的含金属元素层 电介质膜。 位于存储栅电极下方的半导体区域和第二电介质膜的电荷密度低于位于选择栅电极和第一电介质膜下方的半导体区域的电荷密度。

公开(公告)号：US20110039385A1

公开(公告)日：2011-02-17

申请号：US12912609

申请日：2010-10-26

申请人： Yasuhiro Shimamoto ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shinichiro Kimura

发明人： Yasuhiro Shimamoto ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shinichiro Kimura

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  G11C16/0425 ,  H01L21/28282 ,  H01L21/31155 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/66833

摘要： Performance and reliability of a semiconductor device including a non-volatile memory are improved. A memory cell of the non-volatile memory includes, over an upper portion of a semiconductor substrate, a select gate electrode formed via a first dielectric film and a memory gate electrode formed via a second dielectric film formed of an ONO multilayered film having a charge storing function. The first dielectric film functions as a gate dielectric film, and includes a third dielectric film made of silicon oxide or silicon oxynitride and a metal-element-containing layer made of a metal oxide or a metal silicate formed between the select gate electrode and the third dielectric film. A semiconductor region positioned under the memory gate electrode and the second dielectric film has a charge density of impurities lower than that of a semiconductor region positioned under the select gate electrode and the first dielectric film.

摘要翻译： 提高了包括非易失性存储器的半导体器件的性能和可靠性。 非易失性存储器的存储单元包括在半导体衬底的上部上的经由第一电介质膜形成的选择栅电极和通过由具有电荷的ONO多层膜形成的第二电介质膜形成的存储栅电极 存储功能。 第一介质膜用作栅极电介质膜，并且包括由氧化硅或氮氧化硅制成的第三电介质膜和由选择栅电极和第三电极之间形成的金属氧化物或金属硅酸盐构成的含金属元素层 电介质膜。 位于存储栅电极下方的半导体区域和第二电介质膜的电荷密度低于位于选择栅电极和第一电介质膜下方的半导体区域的电荷密度。

公开(公告)号：US07872298B2

公开(公告)日：2011-01-18

申请号：US11777812

申请日：2007-07-13

申请人： Yasuhiro Shimamoto ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shinichiro Kimura

发明人： Yasuhiro Shimamoto ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shinichiro Kimura

IPC分类号： H01L29/788

CPC分类号： H01L29/792 ,  G11C16/0425 ,  H01L21/28282 ,  H01L21/31155 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/66833

摘要： Performance and reliability of a semiconductor device including a non-volatile memory are improved. A memory cell of the non-volatile memory includes, over an upper portion of a semiconductor substrate, a select gate electrode formed via a first dielectric film and a memory gate electrode formed via a second dielectric film formed of an ONO multilayered film having a charge storing function. The first dielectric film functions as a gate dielectric film, and includes a third dielectric film made of silicon oxide or silicon oxynitride and a metal-element-containing layer made of a metal oxide or a metal silicate formed between the select gate electrode and the third dielectric film. A semiconductor region positioned under the memory gate electrode and the second dielectric film has a charge density of impurities lower than that of a semiconductor region positioned under the select gate electrode and the first dielectric film.

摘要翻译： 提高了包括非易失性存储器的半导体器件的性能和可靠性。 非易失性存储器的存储单元包括在半导体衬底的上部上的经由第一电介质膜形成的选择栅电极和通过由具有电荷的ONO多层膜形成的第二电介质膜形成的存储栅电极 存储功能。 第一介质膜用作栅极电介质膜，并且包括由氧化硅或氮氧化硅制成的第三电介质膜和由选择栅电极和第三电极之间形成的金属氧化物或金属硅酸盐构成的含金属元素层 电介质膜。 位于存储栅电极下方的半导体区域和第二电介质膜的电荷密度低于位于选择栅电极和第一电介质膜下方的半导体区域的电荷密度。

公开(公告)号：US20080029805A1

公开(公告)日：2008-02-07

申请号：US11777812

申请日：2007-07-13

申请人： Yasuhiro SHIMAMOTO ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shinichiro Kimura

发明人： Yasuhiro SHIMAMOTO ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shinichiro Kimura

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/792 ,  G11C16/0425 ,  H01L21/28282 ,  H01L21/31155 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/66833

摘要： Performance and reliability of a semiconductor device including a non-volatile memory are improved. A memory cell of the non-volatile memory includes, over an upper portion of a semiconductor substrate, a select gate electrode formed via a first dielectric film and a memory gate electrode formed via a second dielectric film formed of an ONO multilayered film having a charge storing function. The first dielectric film functions as a gate dielectric film, and includes a third dielectric film made of silicon oxide or silicon oxynitride and a metal-element-containing layer made of a metal oxide or a metal silicate formed between the select gate electrode and the third dielectric film. A semiconductor region positioned under the memory gate electrode and the second dielectric film has a charge density of impurities lower than that of a semiconductor region positioned under the select gate electrode and the first dielectric film.

摘要翻译： 提高了包括非易失性存储器的半导体器件的性能和可靠性。 非易失性存储器的存储单元包括在半导体衬底的上部上的经由第一电介质膜形成的选择栅电极和通过由具有电荷的ONO多层膜形成的第二电介质膜形成的存储栅电极 存储功能。 第一介质膜用作栅极电介质膜，并且包括由氧化硅或氮氧化硅制成的第三电介质膜和由选择栅电极和第三电极之间形成的金属氧化物或金属硅酸盐构成的含金属元素层 电介质膜。 位于存储栅电极下方的半导体区域和第二电介质膜的电荷密度低于位于选择栅电极和第一电介质膜下方的半导体区域的电荷密度。

公开(公告)号：US20090231921A1

公开(公告)日：2009-09-17

申请号：US12389361

申请日：2009-02-19

申请人： Shinichiro Kimura ,  Yasuhiro Shimamoto ,  Digh Hisamoto

发明人： Shinichiro Kimura ,  Yasuhiro Shimamoto ,  Digh Hisamoto

IPC分类号： G11C16/06 ,  H01L21/336 ,  H01L29/792 ,  G11C5/14

CPC分类号： H01L27/11568 ,  H01L29/42328 ,  H01L29/792

摘要： In a nonvolatile semiconductor storage device having a split-gate memory cell including a control gate electrode and a sidewall memory gate electrode and a single-gate memory cell including a single memory gate electrode on the same silicon substrate, the control gate electrode is formed in a first region via a control gate insulating film, the sidewall memory gate electrode is formed in the first region via a charge trapping film, and at the same time, a single memory gate electrode is formed in a second region via the charge trapping film. At this time, the sidewall memory gate electrode and the single memory gate electrode are formed in the same process, and the control gate electrode and the sidewall memory gate electrode are formed so as to be adjacently disposed to each other in a state of being electrically isolated from each other.

摘要翻译： 在具有包括控制栅电极和侧壁存储栅电极的分闸存储单元的非易失性半导体存储器件和在同一硅衬底上包括单个存储栅电极的单栅极存储单元中，形成控制栅电极 经由控制栅极绝缘膜的第一区域，所述侧壁存储栅电极经由电荷捕获膜形成在所述第一区域中，并且同时经由电荷捕获膜在第二区域中形成单个存储器栅电极。 此时，侧壁存储器栅极电极和单个存储器栅极电极以相同的工艺形成，并且控制栅极电极和侧壁存储栅电极形成为在电气的状态下彼此相邻地设置 彼此隔离

公开(公告)号：US20090152619A1

公开(公告)日：2009-06-18

申请号：US12368538

申请日：2009-02-10

申请人： DIGH HISAMOTO ,  Kan Yasui ,  Shinichiro Kimura ,  Tetsuya Ishimaru

发明人： DIGH HISAMOTO ,  Kan Yasui ,  Shinichiro Kimura ,  Tetsuya Ishimaru

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  G11C16/0433 ,  H01L21/2815 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/1203 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

摘要： Provided is a nonvolatile semiconductor memory device having a split gate structure, wherein a memory gate is formed over a convex shaped substrate and side surfaces of it is used as a channel. The nonvolatile semiconductor memory device according to the present invention is excellent in read current driving power even if a memory cell is scaled down.

摘要翻译： 提供了一种具有分割栅极结构的非易失性半导体存储器件，其中存储栅极形成在凸形基板上，并且其侧表面用作沟道。 根据本发明的非易失性半导体存储器件即使存储单元按比例缩小，读取电流驱动功率也优异。

公开(公告)号：US20090014775A1

公开(公告)日：2009-01-15

申请号：US12233670

申请日：2008-09-19

申请人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

发明人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

IPC分类号： H01L29/00

CPC分类号： G11C16/0425 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459

摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

摘要翻译： 提供一种稳定运行半导体非易失性存储器件的操作方案。 当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。 因此，可以验证擦除状态，而不知道任何时变变化。 此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

公开(公告)号：US20070183206A1

公开(公告)日：2007-08-09

申请号：US11727592

申请日：2007-03-27

申请人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

发明人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/0425 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459

摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes. Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

摘要翻译： 提供一种稳定运行半导体非易失性存储器件的操作方案。 当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。 因此，可以验证擦除状态，而不知道任何时变变化。 此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

公开(公告)号：US20100322013A1

公开(公告)日：2010-12-23

申请号：US12873679

申请日：2010-09-01

申请人： Tetsuya Ishimaru ,  Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura

发明人： Tetsuya Ishimaru ,  Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura

IPC分类号： G11C16/04 ,  H01L29/792

CPC分类号： G11C16/0466 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/792

摘要： In a situation where a memory cell includes an ONO film, which comprises a silicon nitride film for charge storage and oxide films positioned above and below the silicon nitride film; a memory gate above the ONO film; a select gate, which is adjacent to a lateral surface of the memory gate via the ONO film; a gate insulator positioned below the select gate; a source region; and a drain region, an erase operation is performed by injecting holes generated by BTBT into the silicon nitride film while applying a positive potential to the source region, applying a negative potential to the memory gate, applying a positive potential to the select gate, and flowing a current from the drain region to the source region, thus improving the characteristics of a nonvolatile semiconductor memory device.

摘要翻译： 在存储单元包括ONO膜的情况下，其包括用于电荷存储的氮化硅膜和位于氮化硅膜上方和下方的氧化膜; 在ONO电影上方的记忆门; 选择栅极，其经由ONO膜与存储栅的侧表面相邻; 位于选择门下方的栅极绝缘体; 源区; 和漏极区域，通过将BTBT产生的空穴注入氮化硅膜，同时向源极区域施加正电位，向存储栅极施加负电位，向选择栅极施加正电位，进行擦除操作，以及 使电流从漏极区域流向源极区域，从而改善非易失性半导体存储器件的特性。

公开(公告)号：US07847343B2

公开(公告)日：2010-12-07

申请号：US12368538

申请日：2009-02-10

申请人： Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura ,  Tetsuya Ishimaru

发明人： Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura ,  Tetsuya Ishimaru

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  G11C16/0433 ,  H01L21/2815 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/1203 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

摘要： Provided is a nonvolatile semiconductor memory device having a split gate structure, wherein a memory gate is formed over a convex shaped substrate and side surfaces of it is used as a channel. The nonvolatile semiconductor memory device according to the present invention is excellent in read current driving power even if a memory cell is scaled down.

摘要翻译： 提供了一种具有分割栅极结构的非易失性半导体存储器件，其中存储栅极形成在凸形基板上，并且其侧表面用作沟道。 根据本发明的非易失性半导体存储器件即使存储单元按比例缩小也具有优异的读取电流驱动功率。