公开(公告)号：US5825707A

公开(公告)日：1998-10-20

申请号：US882393

申请日：1997-07-10

申请人： Yasumitsu Nozawa ,  Kenichi Nakamura ,  Takayuki Otani ,  Makoto Segawa

发明人： Yasumitsu Nozawa ,  Kenichi Nakamura ,  Takayuki Otani ,  Makoto Segawa

IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C11/407 ,  H01L21/822 ,  H01L21/8244 ,  H01L27/04 ,  H01L27/11 ,  G11C7/00

CPC分类号： G11C5/14 ,  G11C5/145

摘要： A semiconductor device comprises: a first circuit (11) formed in a first well (N-type) and a second well (P-type) of a semiconductor substrate, supplied with a first supply voltage (V.sub.ss) and a second supply voltage (V.sub.cc) higher than the first supply voltage, and activated when a first well bias voltage (V.sub.BP1) is applied to the first well (N-type) and a second well bias voltage (V.sub.BN1) is applied to the second well (P-type); a second circuit (201; 202) formed in a third well (N-type) and a fourth well (P-type) of the same semiconductor substrate as above, supplied with the first supply voltage (V.sub.ss) and a third supply voltage (V.sub.cc2) higher than the first supply voltage but different from the second supply voltage (V.sub.cc), and activated when a third well bias voltage (V.sub.BP2) is applied to the third well (N-type) and a fourth well bias voltage (V.sub.BN2) is applied to the fourth well (P-type); a first bias circuit (20) supplied with the first and second supply voltages (V.sub.ss and V.sub.cc), for generating and outputting the first well bias voltage (V.sub.BP1); a second bias circuit (21) supplied with the first and second supply voltages (V.sub.ss and V.sub.cc), for generating and outputting the second well bias voltage (V.sub.BN1); a third bias circuit (16) supplied with the first and third supply voltages (V.sub.ss and V.sub.cc2) for generating and outputting the third well bias voltage (V.sub.BP2); and a fourth bias circuit (17) supplied with the first and third supply voltages (V.sub.ss and V.sub.cc2) for generating and outputting the fourth well bias voltage (V.sub.BN2). In the semiconductor device, even if any of the second supply voltage (V.sub.cc) and the third supply voltage (V.sub.cc2) is first supplied, it is possible to prevent the latch-up phenomenon caused by the floated substrate potential.

摘要翻译： 半导体器件包括：形成在半导体衬底的第一阱（N型）和第二阱（P型）中的第一电路，被提供有第一电源电压（Vss）和第二电源电压（ Vcc）高于第一电源电压，并且当第一阱偏压（VBP1）施加到第一阱（N型）并且第二阱偏置电压（VBN1）施加到第二阱（P型）时被激活 ）; 形成在与上述相同的半导体衬底的第三阱（N型）和第四阱（P型）中的第二电路（201; 202）被提供有第一电源电压（Vss）和第三电源电压 Vcc2）高于第一电源电压但不同于第二电源电压（Vcc），并且当第三阱偏压（VBP2）施加到第三阱（N型）和第四阱偏置电压（VBN2）时被激活， 应用于第四井（P型）; 提供有第一和第二电源电压（Vss和Vcc）的第一偏置电路（20），用于产生和输出第一阱偏置电压（VBP1）; 提供有第一和第二电源电压（Vss和Vcc）的第二偏置电路（21），用于产生和输出第二阱偏置电压（VBN1）; 提供有用于产生和输出第三阱偏置电压（VBP2）的第一和第三电源电压（Vss和Vcc2）的第三偏置电路（16）; 以及第四偏置电路（17），其被提供有用于产生和输出第四阱偏置电压（VBN2）的第一和第三电源电压（Vss和Vcc2）。 在半导体装置中，即使首先提供第二电源电压（Vcc）和第三电源电压（Vcc2）中的任何一个，也可以防止浮置的基板电位引起的闭锁现象。

公开(公告)号：USRE36404E

公开(公告)日：1999-11-23

申请号：US970780

申请日：1997-11-14

申请人： Yasushi Kameda ,  Kenichi Nakamura ,  Hiroshi Takamoto ,  Takayuki Harima ,  Makoto Segawa

发明人： Yasushi Kameda ,  Kenichi Nakamura ,  Hiroshi Takamoto ,  Takayuki Harima ,  Makoto Segawa

IPC分类号： G11C11/41 ,  G11C8/14 ,  G11C11/40 ,  G11C7/00

CPC分类号： G11C8/14

摘要： A semiconductor memory device including a plurality of cell array sections each having a plurality of memory cells disposed in a matrix form, the plurality of cell array sections being juxtaposed in a row direction. Main word lines, are each provided in common for all of the plurality of cell array sections in each row, a row select signal being applied to each main word line. Section word lines are connected to memory cells, in each cell array section at each row, for activating the memory cells. Section select lines are provided for each cell array section, a section selection signal being applied to each section select line. Logical circuits are provided for each cell array section, each logical circuit being connected to each main word line and the section select line, executing a logical operation between the row select signal and the section select signal, and activating the section select line when the logical operation result satisfies a predetermined logical condition. Each logical circuit includes a first inverter, a CMOS type second inverter and an N-channel transistor. Each main word line is connected to the input terminals of the first and second inverters. Each section select line is connected to the drain of the N-type transistor and the source of a P-channel transistor of the second inverter. The gate of the N-channel transistor is connected to the output terminal of the first inverter and each section word line is connected to the source of the N-channel transistor and the output terminal of the second inverter. Bit lines are connected to each memory cell for receiving data from a selected memory cell and outputting the data.

摘要翻译： 一种半导体存储器件，包括多个单元阵列部分，每个单元阵列部分具有以矩阵形式设置的多个存储单元，所述多个单元阵列部分在行方向上并置。 主字线各自为每行中的所有多个单元阵列部分共同设置，行选择信号被应用于每个主字线。 部分字线连接到每行的每个单元阵列部分中的存储单元，用于激活存储单元。 为每个单元阵列区段提供区段选择线，区段选择信号被应用于每个区段选择线。 为每个单元阵列部提供逻辑电路，每个逻辑电路连接到每个主字线和选区线，执行行选择信号和区段选择信号之间的逻辑运算，并且当逻辑 运算结果满足规定的逻辑条件。 每个逻辑电路包括第一反相器，CMOS型第二反相器和N沟道晶体管。 每个主字线连接到第一和第二逆变器的输入端。 各段选择线连接到N型晶体管的漏极和第二反相器的P沟道晶体管的源极。 N沟道晶体管的栅极连接到第一反相器的输出端子，并且每个部分字线连接到N沟道晶体管的源极和第二反相器的输出端子。 位线连接到每个存储器单元，用于从所选存储单元接收数据并输出数据。

公开(公告)号：US5043944A

公开(公告)日：1991-08-27

申请号：US611056

申请日：1990-11-09

申请人： Kenichi Nakamura ,  Makoto Segawa

发明人： Kenichi Nakamura ,  Makoto Segawa

IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C11/417

CPC分类号： G11C7/1057 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106

摘要： A semiconductor memory device includes a memory cell array having a plurality of memory cells, each of the cells being capable of storing a data and being selected by an address; a pair of data lines to which a pair of complementary data from a selected memory cell are imputted; an equalizer for short-circuiting and equalizing the pair of data lines when an equalizing signal is applied; an output circuit for outputting a single signal corresponding to the pair of complementary data from the pair of data lines; a pair of latch circuits provided between the output circuit and the equalizer for the pair of data lines, the pair of latch circuits holding the pair of complementary data; a pair of output buffer circuit provided between the pair of latch circuits and the equalizer for the pair of data lines, the pair of output buffer circuits capable of taking a low impedance state wherein the potentials per se of the pair of data lines are outputted, and a high impedance state wherein the potential change of the pair of data lines is not transmitted to the output side of the pair of output buffer circuits; and a controller for generating a first control signal which makes the pair of output buffer circuits to enter the high impedance state before the equalizing signal is applied to the equalizer and a second control signal which makes the pair of output buffer circuits to enter the low impedance state after the equalizing signal is turned off.

公开(公告)号：US5467317A

公开(公告)日：1995-11-14

申请号：US328049

申请日：1994-10-24

申请人： Yasushi Kameda ,  Kenichi Nakamura ,  Hiroshi Takamoto ,  Takayuki Harima ,  Makoto Segawa

发明人： Yasushi Kameda ,  Kenichi Nakamura ,  Hiroshi Takamoto ,  Takayuki Harima ,  Makoto Segawa

IPC分类号： G11C11/41 ,  G11C8/14 ,  G11C11/40 ,  G11C11/34

CPC分类号： G11C8/14

摘要： A semiconductor memory device including a plurality of cell array sections each having a plurality of memory cells disposed in a matrix form, the plurality of cell array sections being juxtaposed in a row direction. Main word lines, are each provided in common for all of the plurality of cell array sections in each row, a row select signal being applied to each main word line. Section word lines are connected to memory cells, in each cell array section at each row, for activating the memory cells. Section select lines are provided for each cell array section, a section selection signal being applied to each section select line. Logical circuits are provided for each cell array section, each logical circuit being connected to each main word line and the section select line, executing a logical operation between the row select signal and the section select signal, and activating the section select line when the logical operation result satisfies a predetermined logical condition. Each logical circuit includes a first inverter, a CMOS type second inverter and an N-channel transistor. Each main word line is connected to the input terminals of the first and second inverters. Each section select line is connected to the drain of the N-type transistor and the source of a P-channel transistor of the second inverter. The gate of the N-channel transistor is connected to the output terminal of the first inverter and each section word line is connected to the source of the N-channel transistor and the output terminal of the second inverter. Bit lines are connected to each memory cell for receiving data from a selected memory cell and outputting the data.

摘要翻译： 一种半导体存储器件，包括多个单元阵列部分，每个单元阵列部分具有以矩阵形式设置的多个存储单元，所述多个单元阵列部分在行方向上并置。 主字线各自为每行中的所有多个单元阵列部分共同设置，行选择信号被应用于每个主字线。 部分字线连接到每行的每个单元阵列部分中的存储单元，用于激活存储单元。 为每个单元阵列区段提供区段选择线，区段选择信号被应用于每个区段选择线。 为每个单元阵列部提供逻辑电路，每个逻辑电路连接到每个主字线和选区线，执行行选择信号和区段选择信号之间的逻辑运算，并且当逻辑 运算结果满足规定的逻辑条件。 每个逻辑电路包括第一反相器，CMOS型第二反相器和N沟道晶体管。 每个主字线连接到第一和第二逆变器的输入端。 各段选择线连接到N型晶体管的漏极和第二反相器的P沟道晶体管的源极。 N沟道晶体管的栅极连接到第一反相器的输出端子，并且每个部分字线连接到N沟道晶体管的源极和第二反相器的输出端子。 位线连接到每个存储器单元，用于从所选存储单元接收数据并输出数据。

公开(公告)号：US08776961B2

公开(公告)日：2014-07-15

申请号：US13479873

申请日：2012-05-24

申请人： Shunsuke Mori ,  Kenichi Nakamura

发明人： Shunsuke Mori ,  Kenichi Nakamura

IPC分类号： F16F9/34

CPC分类号： B60G17/08 ,  B60G2400/10 ,  B60G2400/204 ,  B60G2400/252 ,  B60G2400/51 ,  B60G2500/10

摘要： A shock absorber includes: at least one cylinder apparatus including a cylinder sealingly containing operating fluid, a piston slidably fittedly inserted in the cylinder to divide an interior of the cylinder into two chambers, and a piston rod coupled to the piston and extending to an outside of the cylinder; and at least one damping force generation mechanism connected to the cylinder apparatus, and capable of generating a damping force to be applied to a flow of the operating fluid caused by a movement of the piston and adjusting the damping force from the outside. The damping force generation mechanism includes a damping valve for generating the damping force, a pilot chamber for applying a pilot pressure by the operating fluid to the damping valve, and a pump for at least supplying or discharging the operating fluid to or from the pilot chamber.

摘要翻译： 减震器包括：至少一个气缸装置，其包括密封地容纳工作流体的气缸，可滑动地嵌合在气缸中以将气缸内部分成两个室的活塞，以及联接到活塞并延伸到外部的活塞杆 的气缸 以及连接到气缸装置的至少一个阻尼力产生机构，并且能够产生施加到由活塞的运动引起的工作流体的流动的阻尼力并且调节来自外部的阻尼力。 阻尼力产生机构包括用于产生阻尼力的阻尼阀，用于通过工作流体向阻尼阀施加先导压力的先导室，以及用于至少将工作流体供给或排出到先导室的泵 。

公开(公告)号：US08603652B2

公开(公告)日：2013-12-10

申请号：US13043692

申请日：2011-03-09

申请人： Tadashi Ishiguro ,  Katsumi Araki ,  Kenichi Nakamura

发明人： Tadashi Ishiguro ,  Katsumi Araki ,  Kenichi Nakamura

IPC分类号： G11B5/716

CPC分类号： G11B5/7023 ,  G11B5/7022 ,  G11B5/7026 ,  G11B5/735 ,  G11B5/738

摘要： An aspect of the present invention relates to a magnetic recording medium comprising on one surface of a nonmagnetic support a nonmagnetic layer containing a nonmagnetic powder and a binder and a magnetic layer containing a ferromagnetic powder and a binder in this order, as well as comprising a backcoat layer on the other surface of the nonmagnetic support. The nonmagnetic layer is a radiation-cured layer formed by curing with radiation a given radiation-curable composition, and the backcoat layer comprises filler particles with an average primary particle diameter, D50, ranging from 0.05 to 1.0 μm, the filler particles being selected from the group consisting of organic polymer particles and inorganic colloidal particles.

摘要翻译： 本发明的一个方面涉及一种在非磁性载体的一个表面上包含非磁性粉末和粘合剂的非磁性层和含有铁磁性粉末和粘合剂的磁性层的磁性记录介质，并且包括一个 背涂层在非磁性载体的另一个表面上。 非磁性层是通过用给定的可辐射固化组合物的辐射固化而形成的辐射固化层，背涂层包含平均初级粒径D50为0.05至1.0μm的填料颗粒，填料颗粒选自 由有机聚合物颗粒和无机胶体颗粒组成的组。

公开(公告)号：US08471484B2

公开(公告)日：2013-06-25

申请号：US13193862

申请日：2011-07-29

申请人： Kiyomi Watanabe ,  Kazuo Sakai ,  Kenichi Nakamura

发明人： Kiyomi Watanabe ,  Kazuo Sakai ,  Kenichi Nakamura

IPC分类号： H05B37/02

CPC分类号： H05H1/46 ,  H01J37/32027 ,  H01J37/32045 ,  H05H2001/4682

摘要： A capacitor is connected between direct current voltage terminals, and inductance means is connected between one end of the capacitor and one of load terminals. In a case in which the direct current voltage exceeds a set value, voltage at both ends of the capacitor is shared by the first and second switching elements that are not electrically conductive; in a case in which the direct current voltage is below the set value, the first and second switching elements are electrically conductive on a periodic basis or as needed to output reversed-polarity voltage between load terminals; and in a case in which the first and second switching elements are turned off, voltage at both ends of the capacitor restricts voltage applied to both ends of the first and second switching elements, during a period in which the first and second feedback rectifier elements are electrically conductive.

摘要翻译： 电容器连接在直流电压端子之间，电感装置连接在电容器的一端和负载端子之间。 在直流电压超过设定值的情况下，电容器两端的电压由不导电的第一和第二开关元件共用， 在直流电压低于设定值的情况下，第一和第二开关元件周期性地导电，或者根据需要在负载端子之间输出反极性电压; 并且在第一和第二开关元件截止的情况下，在第一和第二反馈整流元件是第一和第二反馈整流元件的时段期间，电容器两端的电压限制施加到第一和第二开关元件的两端的电压 导电。

公开(公告)号：US20130142045A1

公开(公告)日：2013-06-06

申请号：US13813535

申请日：2012-02-22

申请人： Kenichi Nakamura ,  Seigo Nakao ,  Toyoki Ue ,  Ryohei Kimura

发明人： Kenichi Nakamura ,  Seigo Nakao ,  Toyoki Ue ,  Ryohei Kimura

IPC分类号： H04W28/02

CPC分类号： H04W28/0289 ,  H04N21/2381 ,  H04N21/6112 ,  H04N21/8456

摘要： Disclosed is a technique for providing a transmission data processing method and the like capable of estimating a communicable band in a heterogeneous multi-radio network at a higher speed and minimizing the deterioration of the video quality even if an unavoidable fluctuation occurs in a band available for transmission. According to the technique, there is provided a transmission data processing method at a stage prior to data transmission by a transmission device 100 for providing the data transmission to a reception device 200 as a communication partner, including: a priority giving step of giving priority to each data of multiple pieces of data, to be transmitted to the reception device, based on a predetermined criterion; a feedback receiving step of receiving, from the reception device, feedback information on data transmitted from the transmission device to the reception device; and a distribution step of distributing, based on the priority and the feedback information received, the multiple pieces of data into a first interface and a second interface used for communication with the reception device.

摘要翻译： 公开了一种用于提供能够以更高速度估计异构多无线电网络中的可通信频带并使视频质量恶化最小化的传输数据处理方法等的技术，即使在可用于 传输。 根据该技术，提供了一种传输数据处理方法，在传输设备100进行数据传输之前的阶段，用于向作为通信伙伴的接收设备200提供数据传输，包括：优先级给予步骤，优先级为 基于预定标准将要发送到接收装置的多条数据的每个数据; 反馈接收步骤，从接收装置接收关于从发送装置发送到接收装置的数据的反馈信息; 以及分配步骤，基于所接收的优先级和反馈信息将所述多条数据分配到用于与所述接收设备通信的第一接口和第二接口。

公开(公告)号：US20120318410A1

公开(公告)日：2012-12-20

申请号：US13581494

申请日：2011-04-07

申请人： Toshimi Tarui ,  Kenichi Nakamura ,  Masashi Sakamoto

发明人： Toshimi Tarui ,  Kenichi Nakamura ,  Masashi Sakamoto

IPC分类号： C22C38/34 ,  C21D8/06 ,  C22C38/24 ,  C22C38/20 ,  C22C38/22 ,  C21D11/00 ,  C22C38/40

CPC分类号： B23D61/185 ,  C21D8/06 ,  C21D9/24 ,  C21D9/525 ,  C21D2211/009 ,  C22C38/001 ,  C22C38/02 ,  C22C38/04 ,  C22C38/18

摘要： Regarding contents of C, Si, Mn and Cr, a value of parameter P represented by the following (equation 1) is 1000 or more. A metallic structure contains wire-drawn pearlite in an area ratio of 98% or more, a diameter is 0.05 mm to 0.18 mm, a tensile strength is 4000 MPa or more, and a twist number in a twist test in which a grip-to-grip distance is 100 mm, and a tension equal to a tensile strength×a cross-sectional area of wire×0.5 is applied, is 5 or more. P=1098×[C]+98×[Si]−20×[Mn]+167×[Cr]  (equation 1) (in the (equation 1), [C], [Si], [Mn] and [Cr] indicate contents (mass %) of C, Si, Mn and Cr, respectively.)

摘要翻译： 关于C，Si，Mn和Cr的含量，由以下（式1）表示的参数P的值为1000以上。 金属结构体包含线状珠光体，面积率为98％以上，直径为0.05mm〜0.18mm，拉伸强度为4000MPa以上，扭曲试验中的捻度为 夹持距离为100mm，施加等于拉伸强度×导线横截面积×0.5的张力为5以上。 （式（1），[C]，[Si]，[Mn]和[C]中的P = 1098×[C] +98×[Si] -20×[Mn] Cr]分别表示C，Si，Mn，Cr的含量（质量％））

公开(公告)号：US08334913B2

公开(公告)日：2012-12-18

申请号：US12834270

申请日：2010-07-12

申请人： Satoshi Sakurai ,  Kenichi Nakamura

发明人： Satoshi Sakurai ,  Kenichi Nakamura

IPC分类号： H04N5/217

CPC分类号： H04N5/37455 ,  H03M1/1019 ,  H03M1/123 ,  H03M1/56 ,  H04N5/3575

摘要： Certain embodiments provide an ADC includes a comparator, a binary counter and a control circuit. The comparator compares a first analog signal voltage with a first reference voltage, and compares a second analog signal voltage with a second reference voltage. The binary counter counts up the clock signal for a first period until the first reference voltage becomes equal to the first analog signal after the comparator starts to compare the first reference voltage with the first analog signal voltage, and inverts a logic level of the count output having a plurality of bits after the first period elapses. The binary counter counts up the clock signal for a second period until the second reference voltage becomes equal to a second analog signal after the comparator starts to compare the second reference voltage with the second analog signal voltage.

摘要翻译： 某些实施例提供的ADC包括比较器，二进制计数器和控制电路。 比较器将第一模拟信号电压与第一参考电压进行比较，并将第二模拟信号电压与第二参考电压进行比较。 二进制计数器对第一周期的时钟信号进行计数，直到比较器开始比较第一参考电压和第一模拟信号电压之后，第一参考电压变为等于第一模拟信号，并且反转计数输出的逻辑电平 在经过第一时间段之后具有多个位。 在比较器开始比较第二参考电压和第二模拟信号电压之后，二进制计数器对时钟信号计数第二个周期，直到第二参考电压变为等于第二模拟信号。