公开(公告)号：US5825707A

公开(公告)日：1998-10-20

申请号：US882393

申请日：1997-07-10

申请人： Yasumitsu Nozawa ,  Kenichi Nakamura ,  Takayuki Otani ,  Makoto Segawa

发明人： Yasumitsu Nozawa ,  Kenichi Nakamura ,  Takayuki Otani ,  Makoto Segawa

IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C11/407 ,  H01L21/822 ,  H01L21/8244 ,  H01L27/04 ,  H01L27/11 ,  G11C7/00

CPC分类号： G11C5/14 ,  G11C5/145

摘要： A semiconductor device comprises: a first circuit (11) formed in a first well (N-type) and a second well (P-type) of a semiconductor substrate, supplied with a first supply voltage (V.sub.ss) and a second supply voltage (V.sub.cc) higher than the first supply voltage, and activated when a first well bias voltage (V.sub.BP1) is applied to the first well (N-type) and a second well bias voltage (V.sub.BN1) is applied to the second well (P-type); a second circuit (201; 202) formed in a third well (N-type) and a fourth well (P-type) of the same semiconductor substrate as above, supplied with the first supply voltage (V.sub.ss) and a third supply voltage (V.sub.cc2) higher than the first supply voltage but different from the second supply voltage (V.sub.cc), and activated when a third well bias voltage (V.sub.BP2) is applied to the third well (N-type) and a fourth well bias voltage (V.sub.BN2) is applied to the fourth well (P-type); a first bias circuit (20) supplied with the first and second supply voltages (V.sub.ss and V.sub.cc), for generating and outputting the first well bias voltage (V.sub.BP1); a second bias circuit (21) supplied with the first and second supply voltages (V.sub.ss and V.sub.cc), for generating and outputting the second well bias voltage (V.sub.BN1); a third bias circuit (16) supplied with the first and third supply voltages (V.sub.ss and V.sub.cc2) for generating and outputting the third well bias voltage (V.sub.BP2); and a fourth bias circuit (17) supplied with the first and third supply voltages (V.sub.ss and V.sub.cc2) for generating and outputting the fourth well bias voltage (V.sub.BN2). In the semiconductor device, even if any of the second supply voltage (V.sub.cc) and the third supply voltage (V.sub.cc2) is first supplied, it is possible to prevent the latch-up phenomenon caused by the floated substrate potential.

摘要翻译： 半导体器件包括：形成在半导体衬底的第一阱（N型）和第二阱（P型）中的第一电路，被提供有第一电源电压（Vss）和第二电源电压（ Vcc）高于第一电源电压，并且当第一阱偏压（VBP1）施加到第一阱（N型）并且第二阱偏置电压（VBN1）施加到第二阱（P型）时被激活 ）; 形成在与上述相同的半导体衬底的第三阱（N型）和第四阱（P型）中的第二电路（201; 202）被提供有第一电源电压（Vss）和第三电源电压 Vcc2）高于第一电源电压但不同于第二电源电压（Vcc），并且当第三阱偏压（VBP2）施加到第三阱（N型）和第四阱偏置电压（VBN2）时被激活， 应用于第四井（P型）; 提供有第一和第二电源电压（Vss和Vcc）的第一偏置电路（20），用于产生和输出第一阱偏置电压（VBP1）; 提供有第一和第二电源电压（Vss和Vcc）的第二偏置电路（21），用于产生和输出第二阱偏置电压（VBN1）; 提供有用于产生和输出第三阱偏置电压（VBP2）的第一和第三电源电压（Vss和Vcc2）的第三偏置电路（16）; 以及第四偏置电路（17），其被提供有用于产生和输出第四阱偏置电压（VBN2）的第一和第三电源电压（Vss和Vcc2）。 在半导体装置中，即使首先提供第二电源电压（Vcc）和第三电源电压（Vcc2）中的任何一个，也可以防止浮置的基板电位引起的闭锁现象。

公开(公告)号：US5459423A

公开(公告)日：1995-10-17

申请号：US77737

申请日：1993-06-18

申请人： Yasumitsu Nozawa ,  Shigeto Mizukami ,  Makoto Segawa

发明人： Yasumitsu Nozawa ,  Shigeto Mizukami ,  Makoto Segawa

IPC分类号： G11C11/41 ,  G05F1/46 ,  G11C7/22 ,  G11C11/407 ,  G11C11/413 ,  H01L27/10 ,  H03K5/13 ,  H04B1/40 ,  H03K5/153 ,  H03K5/159

CPC分类号： G11C7/22 ,  G05F1/466 ,  H03K5/133

摘要： A delay circuit is interposed between first and second circuit systems both driven by a first supply voltage. The delay circuit delays a signal applied by the first circuit system, and then transmits the delayed signal to the second circuit system. In particular, a constant voltage supply circuit generates a second supply voltage (constant voltage) on the basis of the first supply voltage, and supplies the constant voltage to this delay circuit, so that a stable constant delay time can be obtained by the delay circuit without being subjected to the influence of fluctuations of the first supply voltage. All the circuit elements are formed on the same semiconductor substrate. Further, it is preferable to construct the constant voltage supply circuit in such a way that the output voltage thereof is programmable.

摘要翻译： 延迟电路插在由第一电源电压驱动的第一和第二电路系统之间。 延迟电路延迟由第一电路系统施加的信号，然后将延迟的信号发送到第二电路系统。 特别地，恒压电源电路基于第一电源电压产生第二电源电压（恒定电压），并将恒定电压提供给该延迟电路，从而可以通过延迟电路获得稳定的恒定延迟时间 而不受第一电源电压波动的影响。 所有电路元件形成在相同的半导体衬底上。 此外，优选构造恒定电压供给电路，使得其输出电压是可编程的。

公开(公告)号：USRE36404E

公开(公告)日：1999-11-23

申请号：US970780

申请日：1997-11-14

申请人： Yasushi Kameda ,  Kenichi Nakamura ,  Hiroshi Takamoto ,  Takayuki Harima ,  Makoto Segawa

发明人： Yasushi Kameda ,  Kenichi Nakamura ,  Hiroshi Takamoto ,  Takayuki Harima ,  Makoto Segawa

IPC分类号： G11C11/41 ,  G11C8/14 ,  G11C11/40 ,  G11C7/00

CPC分类号： G11C8/14

摘要： A semiconductor memory device including a plurality of cell array sections each having a plurality of memory cells disposed in a matrix form, the plurality of cell array sections being juxtaposed in a row direction. Main word lines, are each provided in common for all of the plurality of cell array sections in each row, a row select signal being applied to each main word line. Section word lines are connected to memory cells, in each cell array section at each row, for activating the memory cells. Section select lines are provided for each cell array section, a section selection signal being applied to each section select line. Logical circuits are provided for each cell array section, each logical circuit being connected to each main word line and the section select line, executing a logical operation between the row select signal and the section select signal, and activating the section select line when the logical operation result satisfies a predetermined logical condition. Each logical circuit includes a first inverter, a CMOS type second inverter and an N-channel transistor. Each main word line is connected to the input terminals of the first and second inverters. Each section select line is connected to the drain of the N-type transistor and the source of a P-channel transistor of the second inverter. The gate of the N-channel transistor is connected to the output terminal of the first inverter and each section word line is connected to the source of the N-channel transistor and the output terminal of the second inverter. Bit lines are connected to each memory cell for receiving data from a selected memory cell and outputting the data.

摘要翻译： 一种半导体存储器件，包括多个单元阵列部分，每个单元阵列部分具有以矩阵形式设置的多个存储单元，所述多个单元阵列部分在行方向上并置。 主字线各自为每行中的所有多个单元阵列部分共同设置，行选择信号被应用于每个主字线。 部分字线连接到每行的每个单元阵列部分中的存储单元，用于激活存储单元。 为每个单元阵列区段提供区段选择线，区段选择信号被应用于每个区段选择线。 为每个单元阵列部提供逻辑电路，每个逻辑电路连接到每个主字线和选区线，执行行选择信号和区段选择信号之间的逻辑运算，并且当逻辑 运算结果满足规定的逻辑条件。 每个逻辑电路包括第一反相器，CMOS型第二反相器和N沟道晶体管。 每个主字线连接到第一和第二逆变器的输入端。 各段选择线连接到N型晶体管的漏极和第二反相器的P沟道晶体管的源极。 N沟道晶体管的栅极连接到第一反相器的输出端子，并且每个部分字线连接到N沟道晶体管的源极和第二反相器的输出端子。 位线连接到每个存储器单元，用于从所选存储单元接收数据并输出数据。

公开(公告)号：US5467317A

公开(公告)日：1995-11-14

申请号：US328049

申请日：1994-10-24

申请人： Yasushi Kameda ,  Kenichi Nakamura ,  Hiroshi Takamoto ,  Takayuki Harima ,  Makoto Segawa

发明人： Yasushi Kameda ,  Kenichi Nakamura ,  Hiroshi Takamoto ,  Takayuki Harima ,  Makoto Segawa

IPC分类号： G11C11/41 ,  G11C8/14 ,  G11C11/40 ,  G11C11/34

CPC分类号： G11C8/14

摘要： A semiconductor memory device including a plurality of cell array sections each having a plurality of memory cells disposed in a matrix form, the plurality of cell array sections being juxtaposed in a row direction. Main word lines, are each provided in common for all of the plurality of cell array sections in each row, a row select signal being applied to each main word line. Section word lines are connected to memory cells, in each cell array section at each row, for activating the memory cells. Section select lines are provided for each cell array section, a section selection signal being applied to each section select line. Logical circuits are provided for each cell array section, each logical circuit being connected to each main word line and the section select line, executing a logical operation between the row select signal and the section select signal, and activating the section select line when the logical operation result satisfies a predetermined logical condition. Each logical circuit includes a first inverter, a CMOS type second inverter and an N-channel transistor. Each main word line is connected to the input terminals of the first and second inverters. Each section select line is connected to the drain of the N-type transistor and the source of a P-channel transistor of the second inverter. The gate of the N-channel transistor is connected to the output terminal of the first inverter and each section word line is connected to the source of the N-channel transistor and the output terminal of the second inverter. Bit lines are connected to each memory cell for receiving data from a selected memory cell and outputting the data.

摘要翻译： 一种半导体存储器件，包括多个单元阵列部分，每个单元阵列部分具有以矩阵形式设置的多个存储单元，所述多个单元阵列部分在行方向上并置。 主字线各自为每行中的所有多个单元阵列部分共同设置，行选择信号被应用于每个主字线。 部分字线连接到每行的每个单元阵列部分中的存储单元，用于激活存储单元。 为每个单元阵列区段提供区段选择线，区段选择信号被应用于每个区段选择线。 为每个单元阵列部提供逻辑电路，每个逻辑电路连接到每个主字线和选区线，执行行选择信号和区段选择信号之间的逻辑运算，并且当逻辑 运算结果满足规定的逻辑条件。 每个逻辑电路包括第一反相器，CMOS型第二反相器和N沟道晶体管。 每个主字线连接到第一和第二逆变器的输入端。 各段选择线连接到N型晶体管的漏极和第二反相器的P沟道晶体管的源极。 N沟道晶体管的栅极连接到第一反相器的输出端子，并且每个部分字线连接到N沟道晶体管的源极和第二反相器的输出端子。 位线连接到每个存储器单元，用于从所选存储单元接收数据并输出数据。

公开(公告)号：US5043944A

公开(公告)日：1991-08-27

申请号：US611056

申请日：1990-11-09

申请人： Kenichi Nakamura ,  Makoto Segawa

发明人： Kenichi Nakamura ,  Makoto Segawa

IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C11/417

CPC分类号： G11C7/1057 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106

摘要： A semiconductor memory device includes a memory cell array having a plurality of memory cells, each of the cells being capable of storing a data and being selected by an address; a pair of data lines to which a pair of complementary data from a selected memory cell are imputted; an equalizer for short-circuiting and equalizing the pair of data lines when an equalizing signal is applied; an output circuit for outputting a single signal corresponding to the pair of complementary data from the pair of data lines; a pair of latch circuits provided between the output circuit and the equalizer for the pair of data lines, the pair of latch circuits holding the pair of complementary data; a pair of output buffer circuit provided between the pair of latch circuits and the equalizer for the pair of data lines, the pair of output buffer circuits capable of taking a low impedance state wherein the potentials per se of the pair of data lines are outputted, and a high impedance state wherein the potential change of the pair of data lines is not transmitted to the output side of the pair of output buffer circuits; and a controller for generating a first control signal which makes the pair of output buffer circuits to enter the high impedance state before the equalizing signal is applied to the equalizer and a second control signal which makes the pair of output buffer circuits to enter the low impedance state after the equalizing signal is turned off.

公开(公告)号：US07169080B2

公开(公告)日：2007-01-30

申请号：US10826102

申请日：2004-04-15

申请人： Jiro Takagi ,  Yasuaki Asaki ,  Nobuyuki Kawaguchi ,  Makoto Segawa ,  Hirosuke Niwa

发明人： Jiro Takagi ,  Yasuaki Asaki ,  Nobuyuki Kawaguchi ,  Makoto Segawa ,  Hirosuke Niwa

IPC分类号： B60W10/04

CPC分类号： F02D41/0087 ,  B60W2510/1005 ,  B60W2520/10 ,  F01L13/0005 ,  F01L2800/00 ,  F02D41/0225 ,  F02D2200/023 ,  F02D2200/024 ,  F02D2200/0404 ,  F02D2200/0406 ,  F02D2200/0414 ,  F02D2200/703 ,  F16H63/50 ,  Y10T477/675 ,  Y10T477/679 ,  Y10T477/68

摘要： A control system for an internal combustion engine having a plurality of cylinders and a switching mechanism for switching between an all-cylinder operation in which all of the plurality of cylinders are operated and a partial-cylinder operation in which at least one of the plurality of cylinders is halted. A condition for performing the partial-cylinder operation is determined, based on the detected operating parameters of the vehicle driven by the engine. A result of the determination is modified so that the partial-cylinder operation may be continued, when the detected operating parameters satisfy a predetermined continuation condition within a predetermined time period from the time a vehicle operating state where the condition for performing the partial-cylinder operation is satisfied, has changed to another vehicle operating state where the condition for performing the partial-cylinder operation is not satisfied.

公开(公告)号：US5661429A

公开(公告)日：1997-08-26

申请号：US423613

申请日：1995-04-17

申请人： Takao Nakajima ,  Takayuki Harima ,  Makoto Segawa

发明人： Takao Nakajima ,  Takayuki Harima ,  Makoto Segawa

IPC分类号： H01L27/06 ,  H01L21/8249 ,  H03K19/013 ,  H03K19/08 ,  H03K19/0944 ,  H03K19/02 ,  H03K17/16 ,  H03K17/60

CPC分类号： H03K19/0136 ,  H03K19/09448

摘要： A BiCMOS circuit includes a CMOS circuit for inverting data applied to an input terminal and a first bipolar transistor, having a base connected to an output point of this CMOS circuit, a collector connected to a power supply voltage and an emitter connected to an output terminal, for charging the output terminal. The BiCMOS circuit also includes a second bipolar transistor, having a collector connected to the output terminal, for discharging the output terminal, a first MOS transistor of a first conductivity type connected in parallel between the base and the collector of the second bipolar transistor and a second MOS transistor of the first conductivity type connected in series with the first MOS transistor and having a gate connected to an output point of the CMOS circuit. The Bi-CMOS circuit further includes a third MOS transistor of the first conductivity type connected between the input terminal and the gate of the first MOS transistor of the first conductivity type and having a gate receiving a first reference voltage, and a fourth MOS transistor of a second conductivity type connected between the first reference voltage and the gate of the first MOS transistor. A large variation width of an output voltage can be ensured, and hence the Bi-CMOS circuit normally operates even at a low voltage without any deterioration in terms of delay time.

摘要翻译： BiCMOS电路包括用于将施加到输入端子的数据反相的CMOS电路和具有连接到该CMOS电路的输出点的基极，连接到电源电压的集电极和连接到输出端子的发射极的第一双极晶体管 ，用于对输出端子充电。 BiCMOS电路还包括第二双极晶体管，其具有连接到输出端子的集电极，用于对输出端子进行放电，第一导电类型的第一MOS晶体管并联连接在第二双极晶体管的基极和集电极之间， 所述第一导电类型的第二MOS晶体管与所述第一MOS晶体管串联连接，并且具有连接到所述CMOS电路的输出点的栅极。 Bi-CMOS电路还包括连接在第一导电类型的第一MOS晶体管的输入端和栅极之间的第一导电类型的第三MOS晶体管，并具有接收第一参考电压的栅极，以及第四MOS晶体管 连接在第一参考电压和第一MOS晶体管的栅极之间的第二导电类型。 可以确保输出电压的大的变化幅度，因此即使在低电压下，Bi-CMOS电路也能正常工作，而且延迟时间方面没有任何劣化。

公开(公告)号：US5097448A

公开(公告)日：1992-03-17

申请号：US405885

申请日：1989-09-11

申请人： Makoto Segawa

发明人： Makoto Segawa

IPC分类号： G11C5/14 ,  G11C11/41 ,  G11C11/412 ,  G11C29/00 ,  H01L21/82 ,  H01L21/8244 ,  H01L27/10 ,  H01L27/11

CPC分类号： G11C29/78 ,  G11C11/41 ,  G11C11/412 ,  G11C29/832 ,  G11C5/14 ,  H01L27/1104

摘要： A memory cell array includes static memory cells arranged in an array of n rows.times.m columns. Each of the memory cells includes MOS transistors formed in a semicondutor substrate and in a corresponding one of well regions of the conductivity type opposite to that of the semiconductor substrate. The well regions are independently formed for each row or for every two or more rows of the memory cell array. The well regions are connected to the respective sources of MOS transistors formed in the well regions. The source and backgate of each of the MOS transistors formed in the well regions are connected to the common source wirings for each of the independently formed well regions. Isolation circuits are respectively connected between the common source wirings for the repective well regions and the power source. A row of the memory cell array to which a defective memory cell is connected is isolated from the power source by means of the isolation circuits.

公开(公告)号：US4578694A

公开(公告)日：1986-03-25

申请号：US429183

申请日：1982-09-30

申请人： Shoji Ariizumi ,  Makoto Segawa

发明人： Shoji Ariizumi ,  Makoto Segawa

IPC分类号： H03K19/0944 ,  H01L27/02 ,  H01L27/088 ,  H02H9/04 ,  H03K19/003 ,  H01L27/04 ,  H01L29/78 ,  H03K17/08 ,  H03K17/687

CPC分类号： H01L27/0883 ,  H01L27/0251 ,  H03K19/00315 ,  H01L2924/0002 ,  H02H9/046

摘要： An integrated circuit serving as an E/D type inverter circuit and provided with a gate-protection circuit. The inverter circuit is constructed of an E type MOSFET having a gate coupled to an input signal and a D type MOSFET which operates as load, and the gate-protective circuit is constructed by a MOSFET which is connected between a power supply and the D type MOSFET and whose gate is connected to the power supply. The gate of the D type MOSFET is protected by the gate-protection circuit even if noise exists on the power supply line.

摘要翻译： 作为E / D型逆变器电路的集成电路，具有栅极保护电路。 逆变器电路由具有耦合到输入信号的栅极的E型MOSFET和作为负载工作的D型MOSFET构成，栅极保护电路由连接在电源和D型之间的MOSFET构成 MOSFET，其栅极连接到电源。 即使电源线上存在噪声，D型MOSFET的栅极也受到栅极保护电路的保护。

公开(公告)号：US4554469A

公开(公告)日：1985-11-19

申请号：US469631

申请日：1983-02-25

申请人： Makoto Segawa ,  Shoji Ariizumi

发明人： Makoto Segawa ,  Shoji Ariizumi

IPC分类号： G11C11/413 ,  G11C8/10 ,  G11C8/18 ,  G11C11/418 ,  H03K5/02 ,  H03K17/06 ,  H03K19/094

CPC分类号： G11C11/418 ,  G11C8/10 ,  G11C8/18

摘要： A semiconductor circuit has a static bootstrap circuit, which includes a first MOS transistor with an input signal supplied to the gate and having the current path connected between a voltage source terminal and a node, a second MOS transistor having the gate connected to receive an inverted form of the input signal after a delay time and having the current path connected between the node and a reference potential terminal and a capacitor connected between the gate of the first MOS transistor and the node. The semiconductor circuit also has a short pulse generator. The bootstrap circuit further includes a third MOS transistor having the current path connected between the output terminal of the short pulse generator and the node and with the input signal supplied to the gate and fourth and fifth MOS transistors having the respective gates connected to the gates of the first and second MOS transistors and the respective current paths connected in series between the voltage source terminal and reference potential terminal.

摘要翻译： 半导体电路具有静态自举电路，其包括第一MOS晶体管，其具有提供给栅极的输入信号，并且具有连接在电压源端子和节点之间的电流路径;第二MOS晶体管，其栅极连接以接收反相 在延迟时间之后输入信号的形式，并且连接在节点和参考电位端之间的电流路径以及连接在第一MOS晶体管的栅极和节点之间的电容器。 半导体电路还具有短脉冲发生器。 自举电路还包括第三MOS晶体管，其具有连接在短脉冲发生器的输出端和节点之间的电流路径以及提供给栅极的输入信号，以及连接到栅极的第四和第五MOS晶体管， 第一和第二MOS晶体管和各个电流路径串联连接在电压源端子和参考电位端子之间。