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    Resistive decoupling of function selection signals from input multiplexers in arithmetic logical units ALU
    1.
    发明授权
    Resistive decoupling of function selection signals from input multiplexers in arithmetic logical units ALU 失效
    功能选择信号在算术逻辑单元ALU中的输入多路复用器的电阻去耦

    公开(公告)号：US6119141A

    公开(公告)日：2000-09-12

    申请号：US73693

    申请日：1998-05-06

    申请人： Yew Keong Chong ,  Prashant Shamarao

    发明人： Yew Keong Chong ,  Prashant Shamarao

    IPC分类号： G06F7/575 ,  G06F7/50 ,  G06F7/38

    CPC分类号： G06F7/575

    摘要： The function selection signal of an ALU is resistively decoupled or serially coupled to the input multiplexers of the ALU. By producing delayed function selection signals and decoupling the delayed function signals from the input multiplexers, the input multiplexers are serially activated. This need not impact the overall speed of the ALUs, since the adders are also serially activated by virtue of the carry signal ripple. However, by resistively decoupling the function selection signal from the input multiplexers, the load seen by the input driver that drives the function selection signal inputs of the multiplexer may be reduced, thereby allowing the least significant bit input multiplexer to be activated more rapidly. Moreover, resistive decoupling may be implemented by polysilicon resistors, thereby allowing metal interconnect layers in the integrated circuit to be used for other purposes.

    摘要翻译： ALU的功能选择信号被电阻去耦或串联耦合到ALU的输入多路复用器。 通过产生延迟的功能选择信号并将延迟的功能信号与输入多路复用器去耦，输入多路复用器被串行激活。 这不需要影响ALU的整体速度，因为加法器也由于进位信号纹波而被串行激活。 然而，通过使功能选择信号与输入多路复用器电阻去耦，可以减少驱动复用器的功能选择信号输入的输入驱动器所看到的负载，从而允许最低有效位输入多路复用器被更快地激活。 此外，电阻去耦可以由多晶硅电阻器实现，从而允许集成电路中的金属互连层用于其它目的。

    Impedance-matched output driver circuits having linear characteristics and enhanced coarse and fine tuning control
    2.
    发明授权
    Impedance-matched output driver circuits having linear characteristics and enhanced coarse and fine tuning control 有权
    具有线性特性和增强的粗调和微调控制的阻抗匹配输出驱动电路

    公开(公告)号：US06894529B1

    公开(公告)日：2005-05-17

    申请号：US10616272

    申请日：2003-07-09

    申请人： Yew-Keong Chong ,  David J. Klein ,  XinXin Shao ,  Prashant Shamarao ,  Brian K. Butka

    发明人： Yew-Keong Chong ,  David J. Klein ,  XinXin Shao ,  Prashant Shamarao ,  Brian K. Butka

    IPC分类号： H03K19/00 ,  H03K17/16 ,  H03K19/003

    CPC分类号： H03K19/0005

    摘要： Impedance-matched output driver circuits include a first totem pole driver stage and a second totem pole driver stage. The first totem pole driver stage includes at least one PMOS pull-up transistor and at least one NMOS pull-down transistor therein that are responsive to a first pull-up signal and a first pull-down signal, respectively. The second totem pole driver stage has at least one NMOS pull-up transistor and at least one PMOS pull-down transistor therein that are responsive to a second pull-up signal and second pull-down signal, respectively. The linearity of the output driver circuit is enhanced by including a first resistive element that extends between the first and second totem pole driver stages. The first resistive element has a first terminal, which is electrically coupled to drain terminals of the at least one PMOS pull-up transistor and the at least one NMOS pull-down transistor in the first totem pole driver stage, and a second terminal, which is electrically coupled to source terminals of the at least one NMOS pull-up transistor and the at least one PMOS pull-down transistor in the second totem pole driver stage.

    摘要翻译： 阻抗匹配的输出驱动器电路包括第一图腾柱驱动器级和第二图腾柱驱动级。 第一图腾柱驱动器级包括分别响应于第一上拉信号和第一下拉信号的至少一个PMOS上拉晶体管和至少一个NMOS下拉晶体管。 第二图腾柱驱动器级具有分别响应于第二上拉信号和第二下拉信号的至少一个NMOS上拉晶体管和至少一个PMOS下拉晶体管。 通过包括在第一和第二图腾柱驱动级之间延伸的第一电阻元件来增强输出驱动器电路的线性度。 第一电阻元件具有第一端子，其电耦合到第一图腾柱驱动器级中的至少一个PMOS上拉晶体管的漏极端子和至少一个NMOS下拉晶体管，以及第二端子，其中 电耦合到第二图腾柱驱动级中的至少一个NMOS上拉晶体管的源极端子和至少一个PMOS下拉晶体管。

    Integrated circuit output buffers having feedback switches therein for reducing simultaneous switching noise and improving impedance matching characteristics
    3.
    发明授权
    Integrated circuit output buffers having feedback switches therein for reducing simultaneous switching noise and improving impedance matching characteristics 有权
    具有反馈开关的集成电路输出缓冲器用于降低同时开关噪声和改善阻抗匹配特性

    公开(公告)号：US06242942B1

    公开(公告)日：2001-06-05

    申请号：US09374630

    申请日：1999-08-16

    申请人： Prashant Shamarao

    发明人： Prashant Shamarao

    IPC分类号： H03K1716

    CPC分类号： H03K17/164

    摘要： Integrated circuit output buffers include pull-down an pull-up circuits and a control circuit that utilizes a preferred feedback circuit to facilitate a reduction in simultaneous-switching noise during pull-down and pull-up operations and also improve the impedance matching characteristics of the output buffers during DC conditions. The preferred feedback circuit also limits the degree to which external noise can influence operation of the control circuit. Each of the pull-down and pull-up circuits may comprise a respective pair of primary and secondary transistors. The pull-down circuit is preferably configured so that the primary and secondary pull-down transistors (e.g., NMOS transistors) are electrically coupled to an output signal line (through an ESD protection resistor) and a first reference signal line (e.g., Vss). The control circuit is designed to activate the pull-down circuit by turning on both the primary and secondary pull-down transistors during a leading portion of the pull-down time interval and by turning off the secondary pull-down transistor during a trailing portion of the pull-down time interval using a first feedback switch that is electrically coupled in series between the output signal line and a gate electrode of the secondary pull-down transistor so that a signal representing a potential of said output signal line can be passed through the first feedback switch to the gate electrode of the secondary pull-down transistor.

    摘要翻译： 集成电路输出缓冲器包括下拉一个上拉电路和一个控制电路，利用优选的反馈电路，以便在下拉和上拉操作期间降低同时开关噪声，并且还提高了 输出缓冲器在直流条件下。 优选的反馈电路还限制外部噪声可以影响控制电路的操作的程度。 每个下拉和上拉电路可以包括相应的一对主晶体管和次级晶体管。 优选地，下拉电路被配置为使得主和次级下拉晶体管（例如，NMOS晶体管）电耦合到输出信号线（通过ESD保护电阻器）和第一参考信号线（例如，Vss） 。 控制电路被设计成通过在下拉时间间隔的引导部分期间导通主和次级下拉晶体管来激活下拉电路，并且在下拉时间间隔的尾部期间关断次级下拉晶体管 所述下拉时间间隔使用电耦合在所述输出信号线和所述次级下拉晶体管的栅电极之间的第一反馈开关，使得表示所述输出信号线的电位的信号可以通过所述第二反馈开关 第一反馈开关到次级下拉晶体管的栅电极。

    Integrated circuit output buffers having control circuits therein that utilize output signal feedback to control pull-up and pull-down time intervals
    5.
    发明授权
    Integrated circuit output buffers having control circuits therein that utilize output signal feedback to control pull-up and pull-down time intervals 失效
    其中具有控制电路的集成电路输出缓冲器利用输出信号反馈来控制上拉和下拉时间间隔

    公开(公告)号：US06356102B1

    公开(公告)日：2002-03-12

    申请号：US09613916

    申请日：2000-07-11

    申请人： David J. Klein ,  Prashant Shamarao

    发明人： David J. Klein ,  Prashant Shamarao

    IPC分类号： H03K1716

    CPC分类号： H03K17/164

    摘要： Integrated circuit output buffers include primary and secondary pull-down transistors and an output signal line electrically coupled to a drain of the primary pull-down transistor and a drain of the secondary pull-down transistor. A preferred control circuit is also provided. The control circuit turns on the primary pull-down transistor during first and second consecutive portions of a pull-down time interval and uses a signal fed back from the output signal line to control the timing of when a gate of the secondary pull-down transistor is electrically connected to a drain of the secondary pull-down transistor during the first portion of the pull-down time interval and also control the timing of when the gate electrode of the secondary pull-down transistor is electrically connected to a source of the secondary pull-down transistor during the second portion of the pull-down time interval. A pull-down portion of the control circuit may include a gate pull-up transistor having a drain electrically connected to the drain of the secondary pull-down transistor and a source electrically connected to a gate of the secondary pull-down transistor, and a gate pull-down transistor having a drain electrically connected to the gate of the secondary pull-down transistor and a source electrically connected to a source of the secondary pull-down transistor. These gate pull-up and pull-down transistors can be utilized to selectively turn on the secondary pull-down transistor during a first leading portion of a pull-down time interval and then turn off the secondary pull-down transistor during a second trailing portion of the pull-down time interval.

    摘要翻译： 集成电路输出缓冲器包括主和次级下拉晶体管以及电耦合到初级下拉晶体管的漏极和次级下拉晶体管的漏极的输出信号线。 还提供了优选的控制电路。 控制电路在下拉时间间隔的第一和第二连续部分期间导通初级下拉晶体管，并且使用从输出信号线反馈的信号来控制次级下拉晶体管的栅极何时 在下拉时间间隔的第一部分期间电连接到次级下拉晶体管的漏极，并且还控制次级下拉晶体管的栅极电连接到次级源的源极的定时 在下拉时间间隔的第二部分期间的下拉晶体管。 控制电路的下拉部分可以包括栅极上拉晶体管，其栅极电连接到次级下拉晶体管的漏极，以及电连接到次级下拉晶体管的栅极的源极，以及 栅极下拉晶体管具有电连接到次级下拉晶体管的栅极的漏极和电连接到次级下拉晶体管的源极的源极。 这些栅极上拉和下拉晶体管可以用于在下拉时间间隔的第一引导部分期间选择性地导通次级下拉晶体管，然后在第二后端部分期间关断次级下拉晶体管 的下拉时间间隔。

    DATA RATE BUFFERING IN DISPLAY PORT LINKS
    7.
    发明申请
    DATA RATE BUFFERING IN DISPLAY PORT LINKS 有权
    显示端口链接中的数据速率缓冲

    公开(公告)号：US20110249192A1

    公开(公告)日：2011-10-13

    申请号：US12756116

    申请日：2010-04-07

    申请人： Prashant Shamarao

    发明人： Prashant Shamarao

    IPC分类号： H04N5/44 ,  H04N7/12

    CPC分类号： G09G5/001 ,  G09G5/005 ,  G09G5/006 ,  G09G5/12 ,  G09G5/393 ,  G09G2330/06 ,  G09G2350/00 ,  G09G2370/10 ,  H04N7/0105

    摘要： Rate matching for use in data links between a source device and a sink device is provided. A rate matching device includes a first-in-first-out (FIFO) buffer having a write pointer and a read pointer; a write control having a write clock to write an input data stream from the source device onto the FIFO buffer using the write pointer; a read control having a read clock to read data from the FIFO buffer using a read pointer, insert data to an output data stream and transmitting the data stream to the sink device; a processor to provide a bit number based on the write clock period and the read clock period, wherein the read control inserts blanking data into the output data stream while the read pointer is stopped in the FIFO buffer to allow the write pointer to move ahead by the bit number provided by the processor. Some embodiments are thus able to avoid buffer overflow or underflow scenarios.

    摘要翻译： 提供了在源设备和宿设备之间的数据链路中使用的速率匹配。 速率匹配装置包括具有写指针和读指针的先进先出（FIFO）缓冲器; 写控制，具有写时钟，用于使用写指针将来自源设备的输入数据流写入FIFO缓冲器; 具有读取时钟的读取控制器，用于使用读取指针从FIFO缓冲器读取数据，将数据插入到输出数据流并将数据流传输到宿设备; 处理器，用于基于写入时钟周期和读取时钟周期提供位数，其中读取控制将消隐数据插入到输出数据流中，同时读取指针停留在FIFO缓冲器中，以允许写指针向前移动 处理器提供的位数。 因此，一些实施例能够避免缓冲器溢出或下溢情况。

    Substrate bias circuit and method for integrated circuit device
    8.
    发明授权
    Substrate bias circuit and method for integrated circuit device 有权
    基板偏置电路及集成电路器件的方法

    公开(公告)号：US07911261B1

    公开(公告)日：2011-03-22

    申请号：US12386128

    申请日：2009-04-13

    申请人： Prashant Shamarao

    发明人： Prashant Shamarao

    IPC分类号： G05F1/10

    CPC分类号： G05F3/08

    摘要： A substrate biasing circuit may include a first pump control circuit that generates a first control signal in response to a first reference voltage and a voltage of a first substrate portion, and includes a first reference generator coupled between a temperature compensated voltage and a reference power supply voltage that varies the first reference voltage in response to the voltage of the first substrate voltage and the temperature compensated voltage. A first clamp circuit may generate a first clamp signal in response to a first limit voltage and the voltage of the first substrate portion, the first limit voltage being a scaled version of the temperature compensated voltage. A first charge pump may pump the first substrate portion in at least a first voltage direction in response to the first control signal, and is prevented from pumping in the first voltage direction in response to the first clamp signal.

    摘要翻译： 衬底偏置电路可以包括第一泵控制电路，其响应于第一参考电压和第一衬底部分的电压产生第一控制信号，并且包括耦合在温度补偿电压和参考电源之间的第一参考发生器 电压，其响应于第一衬底电压和温度补偿电压的电压而改变第一参考电压。 第一钳位电路可以响应于第一限制电压和第一衬底部分的电压而产生第一钳位信号，第一限制电压是温度补偿电压的缩放版本。 响应于第一控制信号，第一电荷泵可以以至少第一电压方向泵送第一衬底部分，并且响应于第一钳位信号而防止在第一电压方向上泵送。

    System and method for transmitting USB data over a DisplayPort transmission link
    10.
    发明授权
    System and method for transmitting USB data over a DisplayPort transmission link 有权
    通过DisplayPort传输链路传输USB数据的系统和方法

    公开(公告)号：US09323698B2

    公开(公告)日：2016-04-26

    申请号：US13241127

    申请日：2011-09-22

    申请人： Ji Park ,  Prashant Shamarao

    发明人： Ji Park ,  Prashant Shamarao

    IPC分类号： G06F3/00 ,  G06F13/14 ,  G09G5/00 ,  H04L29/08 ,  H04L12/40 ,  H04L29/06 ,  G06F13/42

    CPC分类号： G06F13/14 ,  G06F13/4265 ,  G09G5/006 ,  G09G2370/04 ,  G09G2370/045 ,  G09G2370/10 ,  H04L12/4013 ,  H04L67/2823 ,  H04L69/08

    摘要： A data transmission system is provided. The data transmission system includes a source device having a source device controller and a register and a sink device having a sink device controller. The data transmission system also includes a transmission link coupling the source device and the sink device. The transmission link includes a unidirectional main line having a plurality of main link channels, a bidirectional auxiliary line configured to transmit data between the source device and the sink device at a first data rate, and a unidirectional interrupt line. The transmission link is configured to transmit data from the source device to the sink device over one of the main link lines at a second data rate and to transmit data from the sink device to the source device over the auxiliary line at the second data rate. The transmission link may comply with the DisplayPort standard, and the data may be transmitted in accordance with the USB standard.

    摘要翻译： 提供数据传输系统。 数据传输系统包括具有源设备控制器和寄存器的源设备以及具有宿设备控制器的宿设备。 数据传输系统还包括耦合源设备和宿设备的传输链路。 传输链路包括具有多个主链路信道的单向主线，被配置为以第一数据速率在源设备和宿设备之间传输数据的双向辅助线路和单向中断线路。 传输链路被配置为以第二数据速率通过主链路线之一从源设备向宿设备发送数据，并且以第二数据速率通过辅助线路将数据从宿设备传输到源设备。 传输链路可以符合DisplayPort标准，并且数据可以根据USB标准传输。