摘要:
The invention relates to an encoding method for encoding a codeword to obtain a parity code. The code is embedded in the codeword and divides the codeword to have intermediate symbol locations between a first and a second set of data symbols. Each data symbol forms a coefficient. The first and the second set of data symbols and the parity code respectively form a first polynomial (M1(x)), a second polynomial (M2(x)), and a parity code polynomial (R(x)). The method comprises: first, designing a first code generator polynomial (G1(x)); next, dividing M1(x)x4 by G1(x) to obtain a first remainder polynomial (R1(x)); next, generating a second code generator polynomial (G2(x)) from G1(x); next, generating a third polynomial (M3(x)); next, dividing M3(x)x4 by G2(x) to obtain a second remainder polynomial (R2(x)); next, performing an adding procedure to R1(x) and R2(x) to obtain R(x); finally, obtaining the parity code from each coefficient of R(x).
摘要:
The invention relates to an encoding method for encoding a codeword to obtain a parity code. The code is embedded in the codeword and divides the codeword to have intermediate symbol locations between a first and a second set of data symbols. Each data symbol forms a coefficient. The first and the second set of data symbols and the parity code respectively form a first polynomial (M1(x)), a second polynomial (M2(x)), and a parity code polynomial (R(x)). The method comprises: first, designing a first code generator polynomial (G1(x)); next, multiplying M1(x) by x4 and dividing the product of M1(x)*x4 by G1(x) to obtain a first remainder polynomial (R1(x)); next, generating a second code generator polynomial (G2(x)) from G1(x); next, generating a third polynomial (M3(x)); next, multiplying M3(x) by x4 and dividing the product of M3(x)*x4 by G2(x) to obtain a second remainder polynomial (R2(x)); next, performing an adding procedure to R1(x) and R2(x) to obtain R(x); finally, obtaining the parity code from each coefficient of R(x).
摘要:
The invention relates to an encoding method for encoding a codeword to obtain a parity code. The code is embedded in the codeword and divides the codeword to have intermediate symbol locations between a first and a second set of data symbols. Each data symbol forms a coefficient. The first and the second set of data symbols and the parity code respectively form a first polynomial (M1(x)), a second polynomial (M2(x)), and a parity code polynomial (R(x)). The method comprises: first, designing a first code generator polynomial (G1(x)); next, dividing M1(x)x4 by G1(x) to obtain a first remainder polynomial (R1(x)); next, generating a second code generator polynomial (G2(x)) from G1(x); next, generating a third polynomial (M3(x)); next, dividing M3(x)x4 by G2(x) to obtain a second remainder polynomial (R2(x)); next, performing an adding procedure to R1(x) and R2(x) to obtain R(x); finally, obtaining the parity code from each coefficient of R(x).
摘要:
The invention relates to an encoding method for encoding a codeword to obtain a parity code. The code is embedded in the codeword and divides the codeword to have intermediate symbol locations between a first and a second set of data symbols. Each data symbol forms a coefficient. The first and the second set of data symbols and the parity code respectively form a first polynomial (M1(x)), a second polynomial (M2(x)), and a parity code polynomial (R(x)). The method comprises: first, designing a first code generator polynomial (G1(x)); next, dividing M1(x)x4 by G1(x) to obtain a first remainder polynomial (R1(x)); next, generating a second code generator polynomial (G2(x)) from G1(x); next, generating a third polynomial (M3(x)); next, dividing M3(x)x4 by G2(x) to obtain a second remainder polynomial (R2(x)); next, performing an adding procedure to R1(x) and R2(x) to obtain R(x); finally, obtaining the parity code from each coefficient of R(x).
摘要:
A two-dimensional array is stored in a first storage memory. A data accessing direction of the first storage memory is in a row direction. A method for reading data in the two-dimensional array in a column direction contains reading a plurality of data sets in the array from the first storage memory; performing a calculating operation on a first data set of the plurality of data sets; storing remaining data sets of the plurality of data sets into a second storage memory; and sequentially reading and applying the calculating operation on the remaining data sets stored in the second storage memory.
摘要:
An error correction code encoder is provided. A first encoder encodes input information bits and generates first parity check bits. An interleaver interleaves the input information bits and generates permuted information bits. A second encoder encodes the permuted information bits and generates second parity check bits. The interleaver interleaves the input information bits in a window-wise manner so that the input information bits are divided into input information bit windows before being interleaved, and permuted information bit windows having the permuted information bits are generated thereafter. When the input information bit windows are grouped into groups according to different window index characteristics, the window index of each permuted information bit window has the same characteristic as the corresponding input information bit window interleaved therefrom.
摘要:
The invention relates to the processor for performing convolution interleaving/de-interleaving on data symbols on plural original data symbols and convolution de-interleaving on the convolution interleaved data symbols. The processor for performing convolution interleaving on data symbol comprises a memory, an original address generator, and a storage address generator which generates an original address. The storage address generator generates the storage address of each of the stored plural data symbols in the memory according to the original address and a first predetermined sequence, and each of the convolution interleaved data symbols is stored in the memory according to the storage address; furthermore, all stored data symbols in the memory are configured into a circular structure.
摘要:
The invention relates to the processor for performing convolution interleaving/de-interleaving on data symbols on plural original data symbols and convolution de-interleaving on the convolution interleaved data symbols. The processor for performing convolution interleaving on data symbol comprises a memory, an original address generator, and a storage address generator which generates an original address. The storage address generator generates the storage address of each of the stored plural data symbols in the memory according to the original address and a first predetermined sequence, and each of the convolution interleaved data symbols is stored in the memory according to the storage address; furthermore, all stored data symbols in the memory are configured into a circular structure.
摘要:
An error correction code encoder is provided. A first encoder encodes input information bits and generates first parity check bits. An interleaver interleaves the input information bits and generates permuted information bits. A second encoder encodes the permuted information bits and generates second parity check bits. The interleaver interleaves the input information bits in a window-wise manner so that the input information bits are divided into input information bit windows before being interleaved, and permuted information bit windows having the permuted information bits are generated thereafter. When the input information bit windows are grouped into groups according to different window index characteristics, the window index of each permuted information bit window has the same characteristic as the corresponding input information bit window interleaved therefrom.
摘要:
The invention relates to the processor for performing convolution interleaving/de-interleaving on data symbols on plural original data symbols and convolution de-interleaving on the convolution interleaved data symbols. The processor for performing convolution interleaving on data symbol comprises a memory, an original address generator, and a storage address generator which generates an original address. The storage address generator generates the storage address of each of the stored plural data symbols in the memory according to the original address and a first predetermined sequence, and each of the convolution interleaved data symbols is stored in the memory according to the storage address; furthermore, all stored data symbols in the memory are configured into a circular structure.