公开(公告)号：US07285377B2

公开(公告)日：2007-10-23

申请号：US10715616

申请日：2003-11-18

申请人： Yi-Nan Chen ,  Jeng-Ping Lin ,  Chih-Ching Lin ,  Hui-Min Mao

发明人： Yi-Nan Chen ,  Jeng-Ping Lin ,  Chih-Ching Lin ,  Hui-Min Mao

IPC分类号： G03F7/00

CPC分类号： H01L21/76897 ,  H01L21/76885 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10888

摘要： A fabrication method for a damascene bit line contact plug. A semiconductor substrate has a first gate conductive structure, a second gate conductive structure and a source/drain region formed therebetween. A first conductive layer is formed in a space between the first gate conductive structure and the second gate conductive structure to be electrically connected to the source/drain region. An inter-layer dielectric with a planarized surface is formed to cover the first conductive layer, the first gate conductive structure, and the second gate conductive structure. A bit line contact hole is formed in the inter-layer dielectric to expose the top of the first conductive layer. A second conductive layer is formed in the bit line contact hole, in which the combination of the second conductive layer and the first conductive layer serves as a damascene bit line contact plug.

摘要翻译： 镶嵌位线接触插头的制造方法。 半导体衬底具有形成在其间的第一栅极导电结构，第二栅极导电结构和源极/漏极区。 第一导电层形成在第一栅极导电结构和第二栅极导电结构之间的空间中，以电连接到源极/漏极区。 形成具有平坦化表面的层间电介质以覆盖第一导电层，第一栅极导电结构和第二栅极导电结构。 在层间电介质中形成位线接触孔，露出第一导电层的顶部。 第二导电层形成在位线接触孔中，其中第二导电层和第一导电层的组合用作镶嵌位线接触插塞。

公开(公告)号：US07678692B2

公开(公告)日：2010-03-16

申请号：US11564238

申请日：2006-11-28

申请人： Yi-Nan Chen ,  Jeng-Ping Lin ,  Chih-Ching Lin ,  Hui-Min Mao

发明人： Yi-Nan Chen ,  Jeng-Ping Lin ,  Chih-Ching Lin ,  Hui-Min Mao

IPC分类号： H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/76885 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10888

摘要： A fabrication method for a damascene bit line contact plug. A semiconductor substrate has a first gate conductive structure, a second gate conductive structure and a source/drain region formed therebetween. A first conductive layer is formed in a space between the first gate conductive structure and the second gate conductive structure to be electrically connected to the source/drain region. An inter-layer dielectric with a planarized surface is formed to cover the first conductive layer, the first gate conductive structure, and the second gate conductive structure. A bit line contact hole is formed in the inter-layer dielectric to expose the top of the first conductive layer. A second conductive layer is formed in the bit line contact hole, in which the combination of the second conductive layer and the first conductive layer serves as a damascene bit line contact plug.

摘要翻译： 镶嵌位线接触插头的制造方法。 半导体衬底具有形成在其间的第一栅极导电结构，第二栅极导电结构和源极/漏极区。 第一导电层形成在第一栅极导电结构和第二栅极导电结构之间的空间中，以电连接到源极/漏极区。 形成具有平坦化表面的层间电介质以覆盖第一导电层，第一栅极导电结构和第二栅极导电结构。 在层间电介质中形成位线接触孔，露出第一导电层的顶部。 第二导电层形成在位线接触孔中，其中第二导电层和第一导电层的组合用作镶嵌位线接触插塞。

公开(公告)号：US20070099125A1

公开(公告)日：2007-05-03

申请号：US11564238

申请日：2006-11-28

申请人： Yi-Nan Chen ,  Jeng-Ping Lin ,  Chih-Ching Lin ,  Hui-Min Mao

发明人： Yi-Nan Chen ,  Jeng-Ping Lin ,  Chih-Ching Lin ,  Hui-Min Mao

IPC分类号： G03C5/00

CPC分类号： H01L21/76897 ,  H01L21/76885 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10888

摘要： A fabrication method for a damascene bit line contact plug. A semiconductor substrate has a first gate conductive structure, a second gate conductive structure and a source/drain region formed therebetween. A first conductive layer is formed in a space between the first gate conductive structure and the second gate conductive structure to be electrically connected to the source/drain region. An inter-layer dielectric with a planarized surface is formed to cover the first conductive layer, the first gate conductive structure, and the second gate conductive structure. A bit line contact hole is formed in the inter-layer dielectric to expose the top of the first conductive layer. A second conductive layer is formed in the bit line contact hole, in which the combination of the second conductive layer and the first conductive layer serves as a damascene bit line contact plug.

摘要翻译： 镶嵌位线接触插头的制造方法。 半导体衬底具有形成在其间的第一栅极导电结构，第二栅极导电结构和源极/漏极区。 第一导电层形成在第一栅极导电结构和第二栅极导电结构之间的空间中，以电连接到源极/漏极区。 形成具有平坦化表面的层间电介质以覆盖第一导电层，第一栅极导电结构和第二栅极导电结构。 在层间电介质中形成位线接触孔，露出第一导电层的顶部。 第二导电层形成在位线接触孔中，其中第二导电层和第一导电层的组合用作镶嵌位线接触插塞。

公开(公告)号：US06909136B2

公开(公告)日：2005-06-21

申请号：US10604344

申请日：2003-07-14

申请人： Yinan Chen ,  Ming-Cheng Chang ,  Jeng-Ping Lin ,  Tse-Yao Huang ,  Change-Rong Wu ,  Hui-Min Mao

发明人： Yinan Chen ,  Ming-Cheng Chang ,  Jeng-Ping Lin ,  Tse-Yao Huang ,  Change-Rong Wu ,  Hui-Min Mao

IPC分类号： H01L21/108 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

CPC分类号： H01L27/10864 ,  H01L27/10832 ,  H01L29/66181 ,  H01L29/945

摘要： A novel trench-capacitor DRAM cell structure is disclosed. The trench-capacitor DRAM cell of this invention includes an active area island having a horizontal semiconductor surface and a vertical sidewall contiguous with the horizontal semiconductor surface. A pass transistor is disposed at the corner of the active area island. The pass transistor includes a folded gate conductor strip extending from the horizontal semiconductor surface to the vertical sidewall of the active area island, a source formed in the horizontal semiconductor surface, a drain formed in the vertical sidewall, and a gate oxide layer underneath the folded gate conductor strip. The source and drain define a folded channel. The trench-capacitor DRAM cell further includes a trench capacitor that is insulated from the folded gate conductor strip by a trench top oxide (TTO) layer and is coupled to the pass transistor via the drain.

摘要翻译： 公开了一种新颖的沟槽电容器DRAM单元结构。 本发明的沟槽电容器DRAM单元包括具有水平半导体表面的有源区域岛和与水平半导体表面邻接的垂直侧壁。 传输晶体管设置在有源区域岛的拐角处。 传输晶体管包括从水平半导体表面延伸到有源区岛的垂直侧壁的折叠栅极导体条，形成在水平半导体表面中的源，在垂直侧壁中形成的漏极和在折叠的下面的栅极氧化物层 栅极导体条。 源极和漏极限定折叠通道。 沟槽电容器DRAM单元还包括沟槽电容器，其通过沟槽顶部氧化层（TTO）层与折叠的栅极导体条绝缘，并且经由漏极耦合到传输晶体管。

公开(公告)号：US20050012131A1

公开(公告)日：2005-01-20

申请号：US10604344

申请日：2003-07-14

申请人： Yinan Chen ,  Ming-Cheng Chang ,  Jeng-Ping Lin ,  Tse-Yao Huang ,  Chang-Rong Wu ,  Hui-Min Mao

发明人： Yinan Chen ,  Ming-Cheng Chang ,  Jeng-Ping Lin ,  Tse-Yao Huang ,  Chang-Rong Wu ,  Hui-Min Mao

IPC分类号： H01L21/108 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

CPC分类号： H01L27/10864 ,  H01L27/10832 ,  H01L29/66181 ,  H01L29/945

摘要： A novel trench-capacitor DRAM cell structure is disclosed. The trench-capacitor DRAM cell of this invention includes an active area island having a horizontal semiconductor surface and a vertical sidewall contiguous with the horizontal semiconductor surface. A pass transistor is disposed at the corner of the active area island. The pass transistor includes a folded gate conductor strip extending from the horizontal semiconductor surface to the vertical sidewall of the active area island, a source formed in the horizontal semiconductor surface, a drain formed in the vertical sidewall, and a gate oxide layer underneath the folded gate conductor strip. The source and drain define a folded channel. The trench-capacitor DRAM cell further includes a trench capacitor that is insulated from the folded gate conductor strip by a trench top oxide (TTO) layer and is coupled to the pass transistor via the drain.

摘要翻译： 公开了一种新颖的沟槽电容器DRAM单元结构。 本发明的沟槽电容器DRAM单元包括具有水平半导体表面的有源区域岛和与水平半导体表面邻接的垂直侧壁。 传输晶体管设置在有源区域岛的拐角处。 传输晶体管包括从水平半导体表面延伸到有源区岛的垂直侧壁的折叠栅极导体条，形成在水平半导体表面中的源，在垂直侧壁中形成的漏极和在折叠的下面的栅极氧化物层 栅极导体条。 源极和漏极限定折叠通道。 沟槽电容器DRAM单元还包括沟槽电容器，其通过沟槽顶部氧化层（TTO）层与折叠的栅极导体条绝缘，并且经由漏极耦合到传输晶体管。

公开(公告)号：US07009236B2

公开(公告)日：2006-03-07

申请号：US10691173

申请日：2003-10-22

申请人： Yi-Nan Chen ,  Hui-Min Mao ,  Chih-Yuan Hsiao ,  Ming-Cheng Chang

发明人： Yi-Nan Chen ,  Hui-Min Mao ,  Chih-Yuan Hsiao ,  Ming-Cheng Chang

IPC分类号： H01L27/108

CPC分类号： H01L27/10864 ,  H01L27/10867

摘要： A memory device with vertical transistors and deep trench capacitors. The device includes a substrate containing at least one deep trench and a capacitor deposited in the lower portion of the deep trench. A conducting structure, having a first conductive layer and a second conductive layer, is deposited on the trench capacitor. A ring shaped insulator is deposited on the sidewall and between the substrate and the first conductive layer. The first conductive layer is surrounded by the ring shaped insulator, and the second conductive layer is deposited on the first conductive layer and the ring shaped insulator. A diffusion barrier between the second conductive layer and the substrate of the deep trench is deposited on one side of the sidewall of the deep trench. A TTO is deposited on the conducting structure. A control gate is deposited on the TTO.

摘要翻译： 具有垂直晶体管和深沟槽电容器的存储器件。 该器件包括含有至少一个深沟槽和沉积在深沟槽的下部的电容器的衬底。 具有第一导电层和第二导电层的导电结构沉积在沟槽电容器上。 环形绝缘体沉积在侧壁上以及衬底和第一导电层之间。 第一导电层被环形绝缘体包围，并且第二导电层沉积在第一导电层和环形绝缘体上。 在深沟槽的侧壁的一侧上沉积第二导电层和深沟槽的衬底之间的扩散阻挡层。 TTO沉积在导电结构上。 控制门被存放在TTO上。

公开(公告)号：US07195975B2

公开(公告)日：2007-03-27

申请号：US10714001

申请日：2003-11-14

申请人： Tzu-Ching Tsai ,  Yi-Nan Chen ,  Hui-Min Mao

发明人： Tzu-Ching Tsai ,  Yi-Nan Chen ,  Hui-Min Mao

IPC分类号： H01L21/8242 ,  H01L21/20

CPC分类号： H01L21/76897 ,  H01L21/76829 ,  H01L21/76895

摘要： A method of forming a bit line contact via. The method includes providing a substrate having a transistor with a gate electrode, drain region, and source region, forming a conductive layer overlying the drain region, conformally forming an insulating barrier layer overlying the substrate, blanketly forming a dielectric layer overlying the insulating barrier layer, and forming a via through the dielectric layer and insulating barrier layer, exposing the conductive layer.

摘要翻译： 形成位线接触通孔的方法。 该方法包括提供具有晶体管的衬底，该晶体管具有栅极，漏极区和源极区，形成覆盖漏极区的导电层，保形地形成覆盖衬底的绝缘阻挡层，覆盖在绝缘阻挡层上的绝缘层 并且通过介电层和绝缘阻挡层形成通孔，暴露导电层。

公开(公告)号：US07064044B2

公开(公告)日：2006-06-20

申请号：US11019850

申请日：2004-12-21

申请人： Yi-Nan Chen ,  Hui-Min Mao

发明人： Yi-Nan Chen ,  Hui-Min Mao

IPC分类号： H01L21/76

CPC分类号： H01L21/31144 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L21/76802 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming contact holes using a multi-layer hard mask. A substrate with a device region and an alignment region having an opening therein to serve as an alignment mark is provided. A dielectric layer is formed overlying the substrate and fills the opening, followed by the multi-layer hard mask. The multi-layer hard mask over the opening is partially removed and that on the device region is patterned to form a plurality of holes therein and expose the underlying dielectric layer. The exposed dielectric layer on the device region is etched to form the plurality of contact holes therein.

摘要翻译： 一种使用多层硬掩模形成接触孔的方法。 提供了具有器件区域和其中具有开口的对准区域用作对准标记的衬底。 形成覆盖在基板上的电介质层，并填充开口，接着是多层硬掩模。 开口上的多层硬掩模被部分去除，并且在器件区域上被图案化以在其中形成多个孔并且暴露下面的介电层。 在器件区域上暴露的介电层被蚀刻以在其中形成多个接触孔。

公开(公告)号：US06987322B2

公开(公告)日：2006-01-17

申请号：US10923591

申请日：2004-08-20

申请人： Yi-Nan Chen ,  Hui-Min Mao

发明人： Yi-Nan Chen ,  Hui-Min Mao

IPC分类号： H01L23/48

CPC分类号： H01L21/31144 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L21/76802 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming contact holes using a multi-layer hard mask. A substrate with a device region and an alignment region having an opening therein to serve as an alignment mark is provided. A dielectric layer is formed overlying the substrate and fills the opening, followed by the multi-layer hard mask. The multi-layer hard mask over the opening is partially removed and that on the device region is patterned to form a plurality of holes therein and expose the underlying dielectric layer. The exposed dielectric layer on the device region is etched to form the plurality of contact holes therein.

公开(公告)号：US20050167719A1

公开(公告)日：2005-08-04

申请号：US11068173

申请日：2005-02-28

申请人： Yi-Nan Chen ,  Hui-Min Mao ,  Chih-Yuan Hsiao ,  Ming-Cheng Chang

发明人： Yi-Nan Chen ,  Hui-Min Mao ,  Chih-Yuan Hsiao ,  Ming-Cheng Chang

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/10864 ,  H01L27/10867

摘要： A memory device with vertical transistors and deep trench capacitors. The device includes a substrate containing at least one deep trench and a capacitor deposited in the lower portion of the deep trench. A conducting structure, having a first conductive layer and a second conductive layer, is deposited on the trench capacitor. A ring shaped insulator is deposited on the sidewall and between the substrate and the first conductive layer. The first conductive layer is surrounded by the ring shaped insulator, and the second conductive layer is deposited on the first conductive layer and the ring shaped insulator. A diffusion barrier between the second conductive layer and the substrate of the deep trench is deposited on one side of the sidewall of the deep trench. A TTO is deposited on the conducting structure. A control gate is deposited on the TTO.

摘要翻译： 具有垂直晶体管和深沟槽电容器的存储器件。 该器件包括含有至少一个深沟槽和沉积在深沟槽的下部的电容器的衬底。 具有第一导电层和第二导电层的导电结构沉积在沟槽电容器上。 环形绝缘体沉积在侧壁上以及衬底和第一导电层之间。 第一导电层被环形绝缘体包围，并且第二导电层沉积在第一导电层和环形绝缘体上。 在深沟槽的侧壁的一侧上沉积第二导电层和深沟槽的衬底之间的扩散阻挡层。 TTO沉积在导电结构上。 控制门被存放在TTO上。