公开(公告)号：US06291331B1

公开(公告)日：2001-09-18

申请号：US09412654

申请日：1999-10-04

申请人： Ying-Lang Wang ,  Jowei Dun ,  Ming-Jer Lee ,  Tong-Hua Kuan

发明人： Ying-Lang Wang ,  Jowei Dun ,  Ming-Jer Lee ,  Tong-Hua Kuan

IPC分类号： H01L2144

CPC分类号： H01L21/76801 ,  H01L2224/02166 ,  H01L2224/05093

摘要： A new method is provided for the creation of layers of dielectric that are used for metal stack interconnect layers where the metal stack exceeds five layers. A stack of five layers of metal interconnect lines contains one layer of Intra Metal dielectric (ILD) and four layers of Inter Metal dielectric (IMD). One or more of the layers of IMD can be formed in the conventional method. One or more of the layers of IMD can be formed in the conventional method after which a layer of high compressive PECVD is deposited over this one or more layers of IMD. The layer of high compressive PECVD provides a crack resistant film that eliminates the formation of cracks in the surface of the IMD.

摘要翻译： 提供了一种新的方法，用于创建用于金属堆叠互连层的电介质层，其中金属叠层超过五层。 五层金属互连线的堆叠包含一层金属介电介质（ILD）和四层金属间介质（IMD）。 IMD的一个或多个层可以用常规方法形成。 可以以常规方法形成IMD的一个或多个层，之后在该一个或多个IMD层上沉积高压缩PECVD层。 高压缩PECVD层提供了抗裂膜，消除了在IMD表面形成裂缝。

公开(公告)号：US06531382B1

公开(公告)日：2003-03-11

申请号：US10140662

申请日：2002-05-08

申请人： Tao Cheng ,  Wen-Hsin Huang ,  Jiun-Pyng You ,  Lin-June Wu ,  Shih-Tzung Chang ,  Ming-Jei Lee ,  Chun-Chang Chen ,  Yu-Ku Lin ,  Tong-Hua Kuan ,  Ying-Lang Wang

发明人： Tao Cheng ,  Wen-Hsin Huang ,  Jiun-Pyng You ,  Lin-June Wu ,  Shih-Tzung Chang ,  Ming-Jei Lee ,  Chun-Chang Chen ,  Yu-Ku Lin ,  Tong-Hua Kuan ,  Ying-Lang Wang

IPC分类号： H01L213205

CPC分类号： H01L21/76802 ,  H01L21/76838

摘要： A process for preparing a surface of a lower level metal structure, exposed at the bottom of a sub-micron diameter opening, to allow a low resistance interface to be obtained when overlaid with an upper level metal structure, has been developed. A disposable, capping insulator layer is first deposited on the composite insulator layer in which the sub-micron diameter opening will be defined in, to protect underlying components of the composite insulator from a subsequent metal pre-metal procedure. After anisotropically defining the sub-micron diameter opening in the capping insulator, and composite insulator layers, and after removal of the defining photoresist shape, an argon sputtering procedure is used to remove native oxide from the surface of the lower level metal structure. In addition to native oxide removal the argon sputtering procedure, featuring a negative DC bias applied to the substrate, also removes the capping insulator layer from the top surface of the composite insulator layer. An in situ metal deposition then allows a clean interface to result between the overlying metal layer, and the underlying plasma treated, metal surface.

摘要翻译： 已经开发了制备在亚微米直径开口的底部露出的下层金属结构的表面以允许在与上层金属结构重叠时获得低电阻界面的方法。 首先将一次性封盖绝缘体层沉积在复合绝缘体层上，在该复合绝缘层上将限定亚微米直径的开口，以保护复合绝缘子的下面的部件免于后续的金属预金属工艺。 在各向异性地限定封盖绝缘体中的亚微米直径开口和复合绝缘体层之后，并且在去除限定的光致抗蚀剂形状之后，使用氩溅射方法从下层金属结构的表面去除自然氧化物。 除了自然氧化物除去之外，具有施加到衬底的负DC偏压的氩溅射工艺也从复合绝缘体层的顶表面去除封盖绝缘体层。 原位金属沉积然后允许在上覆的金属层和下面的等离子体处理的金属表面之间产生干净的界面。

公开(公告)号：US06645825B1

公开(公告)日：2003-11-11

申请号：US09614554

申请日：2000-07-12

申请人： Chin Kun Lan ,  Ting Chun Wang ,  Tong-Hua Kuan ,  Ying-Lang Wang

发明人： Chin Kun Lan ,  Ting Chun Wang ,  Tong-Hua Kuan ,  Ying-Lang Wang

IPC分类号： H01L2176

CPC分类号： H01L21/76229

摘要： An improved and new process for fabricating a planarized structure of shallow trench isolation (STI) embedded in a silicon substrate has been developed. The planarizing method comprises a two-step CMP process in which the first CMP step comprises chemical-mechanical polishing of silicon oxide using a first polishing slurry which is selective to silicon oxide. The time of the second CMP step is determined by selecting an overpolish thickness based on the percentage of substrate area occupied by the trench. High manufacturing yield and superior planarity for silicon oxide STI are achieved.

摘要翻译： 已经开发了一种用于制造嵌入硅衬底中的浅沟槽隔离（STI）的平面化结构的改进和新工艺。 平面化方法包括两步CMP工艺，其中第一CMP步骤包括使用对氧化硅选择性的第一抛光浆料进行二氧化硅的化学机械抛光。 通过基于沟槽占据的衬底面积的百分比来选择过抛光厚度来确定第二CMP步骤的时间。 实现了高的制造成品率和优异的氧化硅STI平坦度。

公开(公告)号：US06287172B1

公开(公告)日：2001-09-11

申请号：US09465700

申请日：1999-12-17

申请人： Tong-Hua Kuan ,  Hui-Ling Wang ,  Ying-Lang Wang ,  Chin-Kun Lan

发明人： Tong-Hua Kuan ,  Hui-Ling Wang ,  Ying-Lang Wang ,  Chin-Kun Lan

IPC分类号： B24B100

CPC分类号： B24B37/345 ,  B24B37/0056 ,  B24B37/042 ,  B24D13/142

摘要： A multi-step chemical-mechanical polishing method for improving tungsten chemical-mechanical polishing (CMP) process is provided in the present invention. The method comprises following steps. First, a wafer is placed on a first pad of a CMP system, wherein a head fixes the wafer on the first pad. Then, the head is rotated and the wafer is polished on the first pad by using a tungsten slurry. Next, the wafer is transferred to place on a second pad of the CMP system, wherein the head fixes the wafer on the second pad. Following, the head is rotated and the wafer is polished on the second pad by using the tungsten slurry. Then, the wafer is cleaned on the second pad by using a de-ionic water. Next, the wafer is transferred to place on a third pad of the CMP system, wherein the head fixes the wafer on the third pad. Following, the wafer is cleaned on the third pad by using the de-ionic water. Last, the head is rotated and the wafer is polished on the third pad by using an oxide slurry, wherein a pH value of the tungsten slurry and a pH value of the oxide slurry are opposite.

摘要翻译： 本发明提供了一种用于改善钨化学机械抛光（CMP）工艺的多步化学机械抛光方法。 该方法包括以下步骤。 首先，将晶片放置在CMP系统的第一焊盘上，其中头部将晶片固定在第一焊盘上。 然后，头部旋转，并且通过使用钨浆料在第一焊盘上抛光晶片。 接下来，将晶片转移到CMP系统的第二焊盘上，其中头部将晶片固定在第二焊盘上。 接下来，头部旋转，并且通过使用钨浆料在第二垫上抛光晶片。 然后，通过使用脱离子水在第二焊盘上清洁晶片。 接下来，将晶片转移到CMP系统的第三焊盘上，其中头部将晶片固定在第三焊盘上。 接下来，通过使用去离子水在第三垫上清洁晶片。 最后，旋转头部，通过使用氧化物浆料在第三焊盘上抛光晶片，其中钨浆料的pH值和氧化物浆料的pH值相反。

公开(公告)号：US06248002B1

公开(公告)日：2001-06-19

申请号：US09421509

申请日：1999-10-20

申请人： Hui-Ling Wang ,  Tong-Hua Kuan ,  Ying-Lang Wang ,  Yu-Ku Lin

发明人： Hui-Ling Wang ,  Tong-Hua Kuan ,  Ying-Lang Wang ,  Yu-Ku Lin

IPC分类号： B24B100

CPC分类号： B24B37/042

摘要： A method to prevent the accumulation of particle impurities on the surface of a semiconductor substrate that contains wolfram plugs during the process of polishing the surface of the wafer. The polishing sequence consists of three distinct polishing steps whereby the first two steps use hard polishing pads while the third step uses a soft polishing pad with the application of slurry during the third polish.

摘要翻译： 一种在抛光晶片表面的过程中防止颗粒杂质在含有钨骨塞的半导体衬底表面积聚的方法。 抛光顺序由三个不同的抛光步骤组成，其中前两个步骤使用硬抛光垫，而第三步在第三次抛光期间使用软抛光垫施加浆料。

公开(公告)号：US06551927B1

公开(公告)日：2003-04-22

申请号：US09880920

申请日：2001-06-15

申请人： Dian-Hau Chen ,  Kwang-Ming Lin ,  Yu-Ku Lin ,  Tong-Hua Kuan ,  Jin-Kuen Lan

发明人： Dian-Hau Chen ,  Kwang-Ming Lin ,  Yu-Ku Lin ,  Tong-Hua Kuan ,  Jin-Kuen Lan

IPC分类号： H01L2144

CPC分类号： H01L29/665 ,  H01L21/28518

摘要： A cobalt silicide process having a titanium-rich/titanium nitride capping layer to improve junction leakage is described. Semiconductor device structures to be silicided are formed in and on a semiconductor substrate. A cobalt layer is deposited overlying the semiconductor device structures. A titanium-rich/titanium nitride capping layer is deposited overlying the cobalt layer. Thereafter, a cobalt silicide layer is formed on the semiconductor device structures. The titanium-rich/titanium nitride capping layer and an unreacted portion of the cobalt layer are removed to complete fabrication of the integrated circuit device.

摘要翻译： 描述了具有富钛/氮化钛覆盖层以改善结漏电的硅化钴工艺。 半导体衬底上形成硅化硅半导体器件结构。 覆盖在半导体器件结构上的钴层被沉积。 覆盖在钴层上的富钛/氮化钛覆盖层被沉积。 此后，在半导体器件结构上形成钴硅化物层。 除去富钛/氮化钛覆盖层和钴层的未反应部分以完成集成电路器件的制造。