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18 条记录 (耗时 0.026 秒)

    CoSix process to improve junction leakage
    1.
    发明授权
    CoSix process to improve junction leakage 有权
    CoSix工艺改善结漏

    公开(公告)号：US06551927B1

    公开(公告)日：2003-04-22

    申请号：US09880920

    申请日：2001-06-15

    申请人： Dian-Hau Chen ,  Kwang-Ming Lin ,  Yu-Ku Lin ,  Tong-Hua Kuan ,  Jin-Kuen Lan

    发明人： Dian-Hau Chen ,  Kwang-Ming Lin ,  Yu-Ku Lin ,  Tong-Hua Kuan ,  Jin-Kuen Lan

    IPC分类号： H01L2144

    CPC分类号： H01L29/665 ,  H01L21/28518

    摘要： A cobalt silicide process having a titanium-rich/titanium nitride capping layer to improve junction leakage is described. Semiconductor device structures to be silicided are formed in and on a semiconductor substrate. A cobalt layer is deposited overlying the semiconductor device structures. A titanium-rich/titanium nitride capping layer is deposited overlying the cobalt layer. Thereafter, a cobalt silicide layer is formed on the semiconductor device structures. The titanium-rich/titanium nitride capping layer and an unreacted portion of the cobalt layer are removed to complete fabrication of the integrated circuit device.

    摘要翻译： 描述了具有富钛/氮化钛覆盖层以改善结漏电的硅化钴工艺。 半导体衬底上形成硅化硅半导体器件结构。 覆盖在半导体器件结构上的钴层被沉积。 覆盖在钴层上的富钛/氮化钛覆盖层被沉积。 此后，在半导体器件结构上形成钴硅化物层。 除去富钛/氮化钛覆盖层和钴层的未反应部分以完成集成电路器件的制造。

    Method for field inversion free multiple layer metallurgy VLSI processing
    4.
    发明授权
    Method for field inversion free multiple layer metallurgy VLSI processing 失效
    无反向多层冶金超大规模集成电路处理方法

    公开(公告)号：US5252515A

    公开(公告)日：1993-10-12

    申请号：US743779

    申请日：1991-08-12

    申请人： Lih-Shyng Tsai ,  Jiunn-Jyi Lin ,  Kwang-Ming Lin ,  Shu-Lan Ying

    发明人： Lih-Shyng Tsai ,  Jiunn-Jyi Lin ,  Kwang-Ming Lin ,  Shu-Lan Ying

    IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/441 ,  H01L21/469

    CPC分类号： H01L21/76834 ,  H01L21/28512 ,  H01L21/76819 ,  H01L21/76828 ,  H01L21/76832 ,  H01L2924/0002 ,  Y10S438/958

    摘要： A multiple layer metallurgy, spin-on-glass multilayer metallurgy structure and method for making such structure for a one micrometer or less feature size integrated circuit with substantially free field inversion on a semiconductor substrate having a pattern of device regions therein. A passivation layer is located over the surfaces of the patterns. A pattern of openings are made through the passivation layer to at least some of the device regions which include source/drain regions. A patterned first metallurgy layer is in contact with the pattern of openings. A first via dielectric layer is located over the pattern of first metallurgy layer. A silicon-rich barrier dielectric layer is located over the first layer. A cured spin-on-glass layer is over the barrier layer. A silicon oxide second via dielectric layer is over the spin-on-glass layer. A pattern of openings is in the second via layer, spin-on-glass layer, barrier layer and first via layer. A patterned second metallurgy layer is in contact with the pattern of openings to make electrical contact with the first metallurgy layer wherein the multilevel metallurgy integrated circuit with substantially free field inversion is completed.

    摘要翻译： 一种多层冶金，旋涂玻璃多层冶金结构和方法，用于在具有其中的器件区域图案的半导体衬底上具有基本自由场反转的1微米或更小的特征尺寸集成电路的这种结构。 钝化层位于图案的表面上方。 通过钝化层将至少一些包含源极/漏极区域的器件区域的开口图案制成。 图案化的第一冶金层与开口图案接触。 第一通孔介电层位于第一冶金层的图案之上。 富硅屏障介电层位于第一层之上。 固化的旋涂玻璃层在阻挡层上。 氧化硅第二通孔电介质层在旋涂玻璃层上方。 开口的图案在第二通孔层，旋涂玻璃层，阻挡层和第一通孔层中。 图案化的第二冶金层与开口图案接触以与第一冶金层电接触，其中完成了具有基本自由场反转的多级冶金集成电路。

    Method of fabricating a node contact
    5.
    发明授权
    Method of fabricating a node contact 失效
    制造节点接触的方法

    公开(公告)号：US06316368B1

    公开(公告)日：2001-11-13

    申请号：US09286080

    申请日：1999-04-05

    申请人： Kwang-Ming Lin ,  Tzu-Min Peng ,  Chieh-Te Chen ,  Pang-Miao Liu

    发明人： Kwang-Ming Lin ,  Tzu-Min Peng ,  Chieh-Te Chen ,  Pang-Miao Liu

    IPC分类号： H01L21302

    CPC分类号： H01L21/31144 ,  H01L21/0332 ,  H01L21/76804 ,  H01L21/76838

    摘要： A method of fabricating a node contact opening is described. A dielectric layer is formed on a substrate. A first conductive layer is formed on the dielectric layer. The first conductive layer is etched to form a trapezoidally cross-sectioned opening exposing a portion of the dielectric layer. The dielectric layer exposed by the trapezoidally cross-sectioned opening is etched to form a node contact opening in the dielectric layer exposing a part the substrate. A second conductive layer is formed to fill the node contact opening and in contact with the conductive layer.

    摘要翻译： 描述了制造节点接触开口的方法。 在基板上形成电介质层。 在介电层上形成第一导电层。 蚀刻第一导电层以形成暴露电介质层的一部分的梯形截面的开口。 蚀刻由梯形截面的开口暴露的电介质层，以在电介质层中形成露出衬底部分的节点接触开口。 形成第二导电层以填充节点接触开口并与导电层接触。

    Nitrogen plasma treatment to prevent field device leakage in VLSI processing
    6.
    发明授权
    Nitrogen plasma treatment to prevent field device leakage in VLSI processing 失效
    氮等离子体处理，以防止VLSI处理中的现场设备泄漏

    公开(公告)号：US5334554A

    公开(公告)日：1994-08-02

    申请号：US825371

    申请日：1992-01-24

    申请人： Kwang-Ming Lin ,  Lih-Shyig Tsai ,  Jiunn-Jyi Lin ,  Yung-Haw Liaw

    发明人： Kwang-Ming Lin ,  Lih-Shyig Tsai ,  Jiunn-Jyi Lin ,  Yung-Haw Liaw

    IPC分类号： H01L21/768 ,  H01L21/469

    CPC分类号： H01L21/76801 ,  H01L21/76819 ,  H01L21/76826 ,  H01L21/76828

    摘要： A method for forming multiple layer metallurgy, spin-on-glass multilayer metallurgy for a one micrometer or less feature size integrated circuit with substantially free field inversion, that is the positive charge between the first via layer and the SOG is described. A semiconductor substrate having a pattern of field effect device source/drain regions therein with a pattern of gate dielectric and gate electrode structures associated therewith and a pattern of field isolation structures at least partially within semiconductor substrate electrically separating certain of these source/drain regions from one another are provided. A passivation layer is formed over the surfaces of said patterns. Then the multilayer metallurgy is formed thereover by opening a pattern of openings through the passivation layer to at least some of the source/drain regions, depositing and patterning a first metallurgy layer in contact with the pattern of openings, forming a first via dielectric layer over the pattern of first metallurgy layer, exposing the first silicon oxide via dielectric layer to a nitrogen plasma, forming a spin-on-glass layer over the via dielectric layer and curing the layer, forming a second via dielectric layer over the spin-on-glass layer, forming a pattern of openings in the second via layer, the spin-on-glass layer, and the first via layer, and depositing and patterning a second metallurgy layer through the openings to make electrical contact with the first metallurgy layer.

    摘要翻译： 描述了一种用于形成具有基本自由场反转的一微米或更小特征尺寸集成电路的多层冶金，旋涂玻璃多层冶金的方法，即第一通孔层和SOG之间的正电荷。 一种具有场效应器件源极/漏极区域的图案的半导体衬底，其栅极电介质和栅极电极结构的图案与其相关联，并且至少部分地在半导体衬底内的场隔离结构的图案将这些源极/漏极区域中的某些从 提供了另一个。 在所述图案的表面上形成钝化层。 然后通过将通过钝化层的开口图案打开到至少一些源极/漏极区域，沉积和图案化与开口图案接触的第一冶金层，从而形成多层冶金，形成第一通孔电介质层 所述第一冶金层的图案，通过介电层将所述第一氧化硅暴露于氮等离子体，在所述通孔电介质层上形成旋涂玻璃层并固化所述层，在所述自旋 - 玻璃层，在第二通孔层，旋涂玻璃层和第一通孔层中形成开口图案，并且通过开口沉积和图案化第二冶金层以与第一冶金层电接触。

    Dielectric ARC scheme to improve photo window in dual damascene process
    9.
    发明授权
    Dielectric ARC scheme to improve photo window in dual damascene process 有权
    介电ARC方案改善双镶嵌工艺中的照片窗口

    公开(公告)号：US06664177B1

    公开(公告)日：2003-12-16

    申请号：US10062645

    申请日：2002-02-01

    申请人： Kwang-Ming Lin ,  Chung-Hung Lu ,  Szu-An Wu ,  Ya-Li Tai ,  Kun-Yi Liu

    发明人： Kwang-Ming Lin ,  Chung-Hung Lu ,  Szu-An Wu ,  Ya-Li Tai ,  Kun-Yi Liu

    IPC分类号： H01L214763

    CPC分类号： H01L21/31144 ,  H01L21/0276 ,  H01L21/76807

    摘要： This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically, to improve the photolithography processing window of a multi-layered dual damascene process by using a dielectric anti-reflective coating, DARC, comprised of multiple layers of silicon oxynitride, SiON, with varying k, dielectric constant values and thickness, to reduce reflectivity and improve light absorption. By varying both the thickness and the dielectric constant of the layers, the optical properties of light absorption, refractive indices, and light reflection are optimized.

    摘要翻译： 本发明涉及用于半导体集成电路器件的制造方法，更具体地说，涉及通过使用由多层硅构成的介电抗反射涂层DARC来改进多层双镶嵌工艺的光刻处理窗口 氧氮化物，SiON，具有不同的k，介电常数值和厚度，以减少反射率并改善光吸收。 通过改变层的厚度和介电常数，优化光吸收，折射率和光反射的光学性质。