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    SUBSTRATE BIAS SWITCHING UNIT FOR A LOW POWER PROCESSOR
    1.
    发明申请
    SUBSTRATE BIAS SWITCHING UNIT FOR A LOW POWER PROCESSOR 失效
    用于低功率处理器的基板偏置开关单元

    公开(公告)号：US20100005324A1

    公开(公告)日：2010-01-07

    申请号：US12346268

    申请日：2008-12-30

    申请人： Yonetaro TOTSUKA ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

    发明人： Yonetaro TOTSUKA ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

    IPC分类号： G06F1/26

    CPC分类号： G06F1/3296 ,  G06F1/3203 ,  Y02D10/172 ,  Y02D50/20

    摘要： The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.

    摘要翻译： 本发明的特征在于：处理器主电路，用于在处理器芯片上执行程序指令串; 衬底偏置切换单元，用于切换施加到处理器主电路的衬底的衬底偏压的电压; 以及操作模式控制单元，用于响应于执行处理器主电路中的待机模式的指令，控制所述衬底偏置切换单元，使得所述偏置切换到所述处理器主电路的电压 待机模式，并且为了响应于来自外部的待机释放的中断来控制衬底偏置切换单元，使得偏置被切换到用于正常模式的电压，并且还用于释放 在切换到其上的偏置电压已经稳定之后，处理器主电路的待机重新开始操作。

    Substrate bias switching unit for a low power processor
    3.
    发明授权
    Substrate bias switching unit for a low power processor 有权
    用于低功耗处理器的基板偏置开关单元

    公开(公告)号：US07475261B2

    公开(公告)日：2009-01-06

    申请号：US10768136

    申请日：2004-02-02

    申请人： Yonetaro Totsuka ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

    发明人： Yonetaro Totsuka ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

    IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F1/32

    CPC分类号： G06F1/3296 ,  G06F1/3203 ,  Y02D10/172 ,  Y02D50/20

    摘要： The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.

    摘要翻译： 本发明的特征在于：处理器主电路，用于在处理器芯片上执行程序指令串; 衬底偏置切换单元，用于切换施加到处理器主电路的衬底的衬底偏压的电压; 以及操作模式控制单元，用于响应于执行处理器主电路中的待机模式的指令，控制所述衬底偏置切换单元，使得所述偏置切换到所述处理器主电路的电压 待机模式，并且为了响应于来自外部的待机释放的中断来控制衬底偏置切换单元，使得偏置被切换到用于正常模式的电压，并且还用于释放 在切换到其上的偏置电压已经稳定之后，处理器主电路的待机重新开始操作。

    Processor for controlling substrate biases in accordance to the operation modes of the processor
    4.
    发明授权
    Processor for controlling substrate biases in accordance to the operation modes of the processor 有权
    用于根据处理器的操作模式控制衬底偏压的处理器

    公开(公告)号：US06715090B1

    公开(公告)日：2004-03-30

    申请号：US09308488

    申请日：1999-05-20

    申请人： Yonetaro Totsuka ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

    发明人： Yonetaro Totsuka ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

    IPC分类号： G06F130

    CPC分类号： G06F1/3296 ,  G06F1/3203 ,  Y02D10/172 ,  Y02D50/20

    摘要： The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.

    摘要翻译： 本发明的特征在于：处理器主电路，用于在处理器芯片上执行程序指令串; 衬底偏置切换单元，用于切换施加到处理器主电路的衬底的衬底偏压的电压; 以及操作模式控制单元，用于响应于执行处理器主电路中的待机模式的指令，控制所述衬底偏置切换单元，使得所述偏置切换到所述处理器主电路的电压 待机模式，并且为了响应于来自外部的待机释放的中断来控制衬底偏置切换单元，使得偏置被切换到用于正常模式的电压，并且还用于释放 在切换到其上的偏置电压已经稳定之后，处理器主电路的待机重新开始操作。

    Substrate bias switching unit for a low power processor
    5.
    发明授权
    Substrate bias switching unit for a low power processor 失效
    用于低功耗处理器的基板偏置开关单元

    公开(公告)号：US07958379B2

    公开(公告)日：2011-06-07

    申请号：US12346268

    申请日：2008-12-30

    申请人： Yonetaro Totsuka ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

    发明人： Yonetaro Totsuka ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

    IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F1/32 ,  B23K11/24

    CPC分类号： G06F1/3296 ,  G06F1/3203 ,  Y02D10/172 ,  Y02D50/20

    摘要： The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.

    摘要翻译： 本发明的特征在于：处理器主电路，用于在处理器芯片上执行程序指令串; 衬底偏置切换单元，用于切换施加到处理器主电路的衬底的衬底偏压的电压; 以及操作模式控制单元，用于响应于执行处理器主电路中的待机模式的指令，控制所述衬底偏置切换单元，使得所述偏置切换到所述处理器主电路的电压 待机模式，并且为了响应于来自外部的待机释放的中断来控制衬底偏置切换单元，使得偏置被切换到用于正常模式的电压，并且还用于释放 在切换到其上的偏置电压已经稳定之后，处理器主电路的待机重新开始操作。

    Data processor and data processor system having multiple modes of address indexing and operation
    6.
    发明授权
    Data processor and data processor system having multiple modes of address indexing and operation 有权
    数据处理器和数据处理器系统具有多种地址索引和操作模式

    公开(公告)号：US06532528B1

    公开(公告)日：2003-03-11

    申请号：US09563753

    申请日：2000-05-01

    申请人： Junichi Nishimoto ,  Osamu Nishii ,  Fumio Arakawa ,  Susumu Narita ,  Masayuki Ito ,  Makoto Toda ,  Kunio Uchiyama

    发明人： Junichi Nishimoto ,  Osamu Nishii ,  Fumio Arakawa ,  Susumu Narita ,  Masayuki Ito ,  Makoto Toda ,  Kunio Uchiyama

    IPC分类号： G06F1210

    CPC分类号： G06F12/1027 ,  G06F2212/652

    摘要： A data processor in which a speed of an address translating operation is raised is disclosed. A translation lookaside buffer is divided into a buffer for data and a buffer for instruction, address translation information for instruction is also stored into a translation lookaside buffer for data, and when a translation miss occurs in a translation lookaside buffer for instruction, new address translation information is fetched from the translation lookaside buffer for data. A high speed of the address translating operation can be realized as compared with that in case of obtaining address translation information from an external address translation table each time a translation miss occurs in the translation lookaside buffer for instruction.

    摘要翻译： 公开了一种提高地址转换操作速度的数据处理器。 翻译后备缓冲区被分为用于数据的缓冲器和用于指令的缓冲器，用于指令的地址转换信息也被存储到用于数据的翻译后备缓冲器中，并且当用于指令的翻译后备缓冲器中发生翻译错误时，新的地址转换 从数据的翻译后备缓冲区中提取信息。 与每次在用于指令的翻译后备缓冲器中发生翻译缺口时从外部地址转换表获得地址转换信息的情况相比，可以实现地址转换操作的高速度。

    Data processor and data processing system having two translation lookaside buffers
    7.
    发明授权
    Data processor and data processing system having two translation lookaside buffers 失效
    具有两个翻译后备缓冲器的数据处理器和数据处理系统

    公开(公告)号：US6092172A

    公开(公告)日：2000-07-18

    申请号：US950668

    申请日：1997-10-15

    申请人： Junichi Nishimoto ,  Osamu Nishii ,  Fumio Arakawa ,  Susumu Narita ,  Masayuki Ito ,  Makoto Toda ,  Kunio Uchiyama

    发明人： Junichi Nishimoto ,  Osamu Nishii ,  Fumio Arakawa ,  Susumu Narita ,  Masayuki Ito ,  Makoto Toda ,  Kunio Uchiyama

    IPC分类号： G06F12/00 ,  G06F13/00

    CPC分类号： G06F12/1027 ,  G06F2212/652

    摘要： A data processor in which a speed of an address translating operation is raised is disclosed. A translation lookaside buffer is divided into a buffer for data and a buffer for instruction, address translation information for instruction is also stored into a translation lookaside buffer for data, and when a translation miss occurs in a translation lookaside buffer for instruction, new address translation information is fetched from the translation lookaside buffer for data. A high speed of the address translating operation can be realized as compared with that in case of obtaining address translation information from an external address translation table each time a translation miss occurs in the translation lookaside buffer for instruction.

    摘要翻译： 公开了一种提高地址转换操作速度的数据处理器。 翻译后备缓冲区被分为用于数据的缓冲器和用于指令的缓冲器，用于指令的地址转换信息也被存储到用于数据的翻译后备缓冲器中，并且当用于指令的翻译后备缓冲器中发生翻译错误时，新的地址转换 从数据的翻译后备缓冲区中提取信息。 与每次在用于指令的翻译后备缓冲器中发生翻译缺口时从外部地址转换表获得地址转换信息的情况相比，可以实现地址转换操作的高速度。

    Data processor having two instruction registers connected in cascade and two instruction decoders
    8.
    发明授权
    Data processor having two instruction registers connected in cascade and two instruction decoders 失效
    数据处理器具有串联连接的两个指令寄存器和两个指令解码器

    公开(公告)号：US5301285A

    公开(公告)日：1994-04-05

    申请号：US940762

    申请日：1992-09-04

    申请人： Makoto Hanawa ,  Osamu Nishii ,  Susumu Narita ,  Kunio Uchiyama

    发明人： Makoto Hanawa ,  Osamu Nishii ,  Susumu Narita ,  Kunio Uchiyama

    IPC分类号： G06F9/34 ,  G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/3822

    摘要： A data processor is provided with a first register storing a first half word of one instruction; a second register storing a second half word of the instruction; a first decoder decoding the first half word and at the same time detecting whether there exists an addressing extension portion between the first half word and the second half word; a second decoder decoding the second half word; and, a decode result generating circuit, to which a detection signal of the first decoder indicates whether the addressing extension portion exists. A decode result of the first decoder and a decode result of the second decoder are supplied to the decode result generating circuit. An extension portion register is provided to store the addressing extension portion. When the first decoder detects the addressing extension portion, the decode result generating circuit invalidates the decode result of the second decoder. On the other hand, in the case where there exists no addressing extension portion, the decode result generating circuit judges, on the basis of the detection signal, that the decode result of the second decoder is valid.

    摘要翻译： 数据处理器设置有存储一个指令的前半字的第一寄存器; 存储指令的第二个半字的第二寄存器; 解码所述前半字，并且同时检测在所述前半字和所述第二半字之间是否存在寻址扩展部分的第一解码器; 解码所述第二半字的第二解码器; 以及第一解码器的检测信号指示寻址扩展部分是否存在的解码结果生成电路。 第一解码器的解码结果和第二解码器的解码结果被提供给解码结果生成电路。 提供扩展部分寄存器以存储寻址扩展部分。 当第一解码器检测到寻址扩展部分时，解码结果生成电路使第二解码器的解码结果无效。 另一方面，在不存在寻址扩展部的情况下，解码结果生成电路根据检测信号判断第二解码器的解码结果有效。

    Semiconductor device
    9.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07254082B2

    公开(公告)日：2007-08-07

    申请号：US11363060

    申请日：2006-02-28

    申请人： Takao Watanabe ,  Kunio Uchiyama ,  Osamu Nishii ,  Naohiko Irie ,  Hiroyuki Mizuno

    发明人： Takao Watanabe ,  Kunio Uchiyama ,  Osamu Nishii ,  Naohiko Irie ,  Hiroyuki Mizuno

    IPC分类号： G11C8/00 ,  G11C5/14

    CPC分类号： G06F1/3203 ,  G06F1/3287 ,  G11C5/147 ,  G11C11/417 ,  Y02D10/171

    摘要： When a leakage current of a circuit block under a non-use state is reduced by means of a power switch, frequent ON/OFF operations of the switch within a short time invite an increase of consumed power, on the contrary. Because a pre-heating time is necessary from turn-on of the switch till the circuit block becomes usable, control of the switch during an operation deteriorates a processing time of a semiconductor device. The switch is ON/OFF-controlled with a task duration time of a CPU core for controlling logic circuits and memory cores as a unit. After the switch is turned off, the switch is again turned on before termination of the task in consideration of the pre-heating time.

    摘要翻译： 相反，当通过电源开关减小不使用状态下的电路块的漏电流时，短时间内开关频繁的接通/断开操作会引起消耗功率的增加。 由于开关的接通需要预热时间，直到电路块变得可用，所以在操作期间的开关的控制使半导体器件的处理时间变差。 该开关通过CPU核心的任务持续时间进行ON / OFF控制，用于将逻辑电路和存储器核心作为一个单元进行控制。 关闭开关后，考虑到预热时间，开关将在任务结束前再次打开。