公开(公告)号：US09413983B2

公开(公告)日：2016-08-09

申请号：US12515747

申请日：2007-11-06

申请人： Yoichiro Sako ,  Keiji Kimura ,  Masaaki Tsuruta ,  Masamichi Asukai ,  Taiji Ito ,  Kan Ebisawa ,  Nozomu Ozaki ,  Akinobu Sugino ,  Hidehiko Sekizawa ,  Yonetaro Totsuka

发明人： Yoichiro Sako ,  Keiji Kimura ,  Masaaki Tsuruta ,  Masamichi Asukai ,  Taiji Ito ,  Kan Ebisawa ,  Nozomu Ozaki ,  Akinobu Sugino ,  Hidehiko Sekizawa ,  Yonetaro Totsuka

IPC分类号： H04N5/225 ,  H04N5/247 ,  H04N7/18 ,  H04N21/218

CPC分类号： H04N7/181 ,  H04N5/2252 ,  H04N5/247 ,  H04N5/38 ,  H04N7/185 ,  H04N21/21805

摘要： The present invention makes it possible to let a user arbitrarily and easily see any other scene than himself or herself in his or her view (the scene seen from any other moving body than him or her). In a display device (an image pickup and display device 1 or a display device 40), specification information is generated to specify a specific image pickup device of outer image pickup devices (the image pickup and display device 1 or and image pickup device 30), and image data are received from the image pickup device specified by the specification information and are displayed. As an outer image pickup device, for example, and image pickup device wore by some other person, image pickup devices set at a car, an electric train, and the like, or further mage pickup devices set at an animal, a bird, and the like are supposed. Image data picked up by these image pickup devices are transmitted to the display side and the image display is carried out in the display device. Thus, a user of the display device can see images of viewing scenes watched by other people, for example, images of viewing scenes seen from a car, an electric train, and the like, or images of viewing scenes seen from an animal, a bird, and the like.

摘要翻译： 本发明使得使用者可以在他或她的观点（从任何其他移动体看到的场景比他或她看到的场景）任意地容易地看到任何其他场景。 在显示装置（图像拾取和显示装置1或显示装置40）中，生成指定信息以指定外部图像拾取装置（图像拾取和显示装置1或图像拾取装置30）的特定图像拾取装置， ，并且从由指定信息指定的图像拾取装置接收图像数据，并显示。 作为外部图像拾取装置，例如，由其他人佩戴的图像拾取装置，设置在汽车的图像拾取装置，电动列车等，或设置在动物，鸟和 应该是这样的。 由这些图像拾取装置拾取的图像数据被发送到显示侧，并且在显示装置中执行图像显示。 因此，显示装置的用户可以看到其他人观看的场景的图像，例如从汽车，电动火车等看到的观看场景的图像，或从动物看到的观看场景的图像， 鸟等。

公开(公告)号：US20100005324A1

公开(公告)日：2010-01-07

申请号：US12346268

申请日：2008-12-30

申请人： Yonetaro TOTSUKA ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

发明人： Yonetaro TOTSUKA ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

IPC分类号： G06F1/26

CPC分类号： G06F1/3296 ,  G06F1/3203 ,  Y02D10/172 ,  Y02D50/20

摘要： The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.

摘要翻译： 本发明的特征在于：处理器主电路，用于在处理器芯片上执行程序指令串; 衬底偏置切换单元，用于切换施加到处理器主电路的衬底的衬底偏压的电压; 以及操作模式控制单元，用于响应于执行处理器主电路中的待机模式的指令，控制所述衬底偏置切换单元，使得所述偏置切换到所述处理器主电路的电压 待机模式，并且为了响应于来自外部的待机释放的中断来控制衬底偏置切换单元，使得偏置被切换到用于正常模式的电压，并且还用于释放 在切换到其上的偏置电压已经稳定之后，处理器主电路的待机重新开始操作。

公开(公告)号：US06243732B1

公开(公告)日：2001-06-05

申请号：US09479075

申请日：2000-01-07

申请人： Fumio Arakawa ,  Norio Nakagawa ,  Tetsuya Yamada ,  Yonetaro Totsuka

发明人： Fumio Arakawa ,  Norio Nakagawa ,  Tetsuya Yamada ,  Yonetaro Totsuka

IPC分类号： G06F732

CPC分类号： G06F7/509 ,  G06F7/483 ,  G06F7/5443 ,  G06F7/548 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/3885 ,  G06F9/3887

摘要： A data processor includes an arithmetic portion incorporated in a floating point unit, in which the arithmetic portion includes a plurality of multipliers supplied mantissa part of floating point number from respectively different data input signal line group and performing mutual multiplication of supplied mantissa parts, an aligner receiving outputs of respective multipliers and performing alignment shift, an exponent processing portion for generating number of alignment shift of the aligner and an exponent before normalization on the basis of generation an exponent part of the floating point number, a multi-input adder and the exponent before normalization, reducing scale of the circuit and performing inner product operation and the like with the floating point numbers in high speed and high accuracy.

摘要翻译： 数据处理器包括并入浮点单元中的算术部分，其中运算部分包括多个乘法器，从分别不同的数据输入信号线组提供浮点数的尾数部分，并执行所提供的尾数部分的相乘;对准器 接收相应乘法器的输出并执行对准移位，指数处理部分，用于基于产生浮点数的指数部分，产生对准器的对准偏移量和归一化前的指数，多输入加法器和指数 在正常化之前，以高速和高精度降低电路的尺寸并且以浮点数进行内部产品操作等。

公开(公告)号：US20110208983A1

公开(公告)日：2011-08-25

申请号：US13101678

申请日：2011-05-05

申请人： Yonetaro TOTSUKA ,  Koichiro ISHIBASHI ,  Hiroyuki MIZUNO ,  Osamu Nishii ,  Kunio UCHIYAMA ,  Takanori SHIMURA ,  Asako SEKINE ,  Yoichi KATSUKI ,  Susumu NARITA

发明人： Yonetaro TOTSUKA ,  Koichiro ISHIBASHI ,  Hiroyuki MIZUNO ,  Osamu Nishii ,  Kunio UCHIYAMA ,  Takanori SHIMURA ,  Asako SEKINE ,  Yoichi KATSUKI ,  Susumu NARITA

IPC分类号： G06F1/26

CPC分类号： G06F1/3296 ,  G06F1/3203 ,  Y02D10/172 ,  Y02D50/20

摘要： The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.

摘要翻译： 本发明的特征在于：处理器主电路，用于在处理器芯片上执行程序指令串; 衬底偏置切换单元，用于切换施加到处理器主电路的衬底的衬底偏压的电压; 以及操作模式控制单元，用于响应于执行处理器主电路中的待机模式的指令，控制所述衬底偏置切换单元，使得所述偏置切换到所述处理器主电路的电压 待机模式，并且为了响应于来自外部的待机释放的中断来控制衬底偏置切换单元，使得偏置被切换到用于正常模式的电压，并且还用于释放 在切换到其上的偏置电压已经稳定之后，处理器主电路的待机重新开始操作。

公开(公告)号：US07551840B2

公开(公告)日：2009-06-23

申请号：US10517073

申请日：2003-05-16

申请人： Fumiyoshi Abe ,  Takuji Himeno ,  Toshinori Kouzai ,  Yonetaro Totsuka

发明人： Fumiyoshi Abe ,  Takuji Himeno ,  Toshinori Kouzai ,  Yonetaro Totsuka

IPC分类号： H04N7/26

CPC分类号： G11B20/1208 ,  G11B27/107 ,  G11B27/3027 ,  G11B27/3063 ,  G11B2220/90 ,  H04N5/782 ,  H04N5/78263 ,  H04N5/783 ,  H04N9/8042 ,  H04N9/8063 ,  H04N9/8205 ,  H04N9/8227

摘要： A video tape recorder for recording high definition television video signals onto a magnetic tape, and recording at least reproduction standard management information in the order of pictures of video data in a main sector, and in the order of pictures of compressed video data in a subcode sector. Search data is recorded on the basis of time management information of video data at the time of decoding, while display data is recorded on the basis of time management information on reproduction and output of video data.

摘要翻译： 一种用于将高分辨率电视视频信号记录到磁带上的磁带录像机，并且至少在主扇区中以视频数据的图像的顺序记录再现标准管理信息，并且按照子代码中的压缩视频数据的图像顺序 部门。 基于解码时的视频数据的时间管理信息记录搜索数据，同时根据关于视频数据的再现和输出的时间管理信息来记录显示数据。

公开(公告)号：US20080259199A1

公开(公告)日：2008-10-23

申请号：US11978407

申请日：2007-10-29

申请人： Yoichiro Sako ,  Keiji Kimura ,  Masaaki Tsuruta ,  Masamichi Asukai ,  Taiji Ito ,  Nozomu Ozaki ,  Akinobu Sugino ,  Hidehiko Sekizawa ,  Yonetaro Totsuka

发明人： Yoichiro Sako ,  Keiji Kimura ,  Masaaki Tsuruta ,  Masamichi Asukai ,  Taiji Ito ,  Nozomu Ozaki ,  Akinobu Sugino ,  Hidehiko Sekizawa ,  Yonetaro Totsuka

IPC分类号： H04N5/222 ,  G06K9/00

CPC分类号： G01C21/36 ,  A63F13/12 ,  G11B27/3027 ,  G11B27/36

摘要： Disclosed herein is an image display system including a display apparatus, an imaging apparatus placed on a movable body; and a server apparatus. The display apparatus and the imaging apparatus are capable of communicating with the server apparatus. The imaging apparatus includes: an imaging section; a speed detection section; and a control section that controls transmission of image data and speed information to the server apparatus. The server apparatus includes: a movable body speed management section that manages the moving speed of the movable body using the speed information; and a control section that identifies an imaging apparatus that matches speed specification information, and causes image data to be transferred from the identified imaging apparatus to the display apparatus. The display apparatus includes: a display section; and a control section that performs a speed specification process, an image request transmission process, and a display process.

摘要翻译： 本文公开了一种图像显示系统，包括显示装置，放置在可移动体上的成像装置; 和服务器装置。 显示装置和成像装置能够与服务器装置进行通信。 成像装置包括：成像部; 速度检测部; 以及控制部，其控制图像数据的传送和速度信息到服务器装置。 服务器装置包括：移动体速度管理部，其使用速度信息来管理移动体的移动速度; 以及控制部分，其识别匹配速度指定信息的成像装置，并且使图像数据从所识别的成像装置传送到显示装置。 显示装置包括：显示部; 以及执行速度指定处理，图像请求发送处理和显示处理的控制部。

公开(公告)号：US06640298B1

公开(公告)日：2003-10-28

申请号：US09544480

申请日：2000-04-07

申请人： Yonetaro Totsuka ,  Yoshio Miki

发明人： Yonetaro Totsuka ,  Yoshio Miki

IPC分类号： G06F938

CPC分类号： G06F9/3848

摘要： A branch prediction apparatus to minimize branch penalties in pipeline or concurrent processing of a sequence of instructions correctly predicts a pattern in which “branch taken” and “branch not taken” alternately appear. The apparatus includes a branch prediction table to keep one history bit and a 2-bit counter for each branch instruction, a prediction generator to output a value of the history bit when the counter has a value of 0 or 2 and to output a value obtained by reversing the history bit when the counter has a value of 1 or 3, and a counter controller which compares a result of branch with a value of the history bit. The counter controller sets 0 to the counter value when the result matches the value and adds one to the counter value when the result does not match the value and the counter value is other than 3.

摘要翻译： 一种分支预测装置，用于最小化流水线中的分支处罚或一系列指令的并发处理，正确地预测了“分支采取”和“不采取分支”交替出现的模式。 该装置包括一个分支预测表，用于保持每个分支指令的一个历史比特和一个2比特的计数器;一个预测发生器，当计数器的值为0或2时输出历史比特的值，并输出获得的值 当计数器的值为1或3时，通过反转历史比特，以及将分支结果与历史比特的值进行比较的计数器控制器。 当结果与值匹配时，计数器控制器将0设置为计数器值，当结果与值不匹配，计数器值不为3时，将计数器值加1。

公开(公告)号：US08364988B2

公开(公告)日：2013-01-29

申请号：US13101678

申请日：2011-05-05

申请人： Yonetaro Totsuka ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

发明人： Yonetaro Totsuka ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F1/32 ,  G06F11/30 ,  H02J1/00

CPC分类号： G06F1/3296 ,  G06F1/3203 ,  Y02D10/172 ,  Y02D50/20

摘要： The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.

公开(公告)号：US07475261B2

公开(公告)日：2009-01-06

申请号：US10768136

申请日：2004-02-02

申请人： Yonetaro Totsuka ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

发明人： Yonetaro Totsuka ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F1/32

CPC分类号： G06F1/3296 ,  G06F1/3203 ,  Y02D10/172 ,  Y02D50/20

摘要： The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.

摘要翻译： 本发明的特征在于：处理器主电路，用于在处理器芯片上执行程序指令串; 衬底偏置切换单元，用于切换施加到处理器主电路的衬底的衬底偏压的电压; 以及操作模式控制单元，用于响应于执行处理器主电路中的待机模式的指令，控制所述衬底偏置切换单元，使得所述偏置切换到所述处理器主电路的电压 待机模式，并且为了响应于来自外部的待机释放的中断来控制衬底偏置切换单元，使得偏置被切换到用于正常模式的电压，并且还用于释放 在切换到其上的偏置电压已经稳定之后，处理器主电路的待机重新开始操作。

公开(公告)号：US20060101108A1

公开(公告)日：2006-05-11

申请号：US10982119

申请日：2004-11-05

申请人： Sang Dhong ,  Christian Jacobi ,  Silvia Mueller ,  Hwa-Joon Oh ,  Yonetaro Totsuka

发明人： Sang Dhong ,  Christian Jacobi ,  Silvia Mueller ,  Hwa-Joon Oh ,  Yonetaro Totsuka

IPC分类号： G06F7/50

CPC分类号： G06F7/49952 ,  G06F7/483

摘要： A method, an apparatus, and a computer program are provided to more efficiently generate a sticky bit in a Floating Point Design. Traditionally, separate ORing logic or OR trees were employed to compress the stick outputs of a normalization shifter into at least one sticky bit. However, this design has power consumption and area costs associated with it. To overcome these disadvantages, the OR trees of Leading Zero Counters (CLZs) are employed in conjunction with the Edge Vector logic of a Leading Sign Anticipator and an additional OR gate to determine the sticky bit.

摘要翻译： 提供了一种方法，装置和计算机程序，以在浮点设计中更有效地生成粘性位。 传统上，使用单独的ORing逻辑或OR树来将归一化移位器的棒输出压缩成至少一个粘性位。 但是，该设计具有与之相关的功耗和面积成本。 为了克服这些缺点，领先的零计数器（CLZ）的OR树结合领先标志预期者的边缘向量逻辑和附加的或门来确定粘滞位。