公开(公告)号：US5301285A

公开(公告)日：1994-04-05

申请号：US940762

申请日：1992-09-04

申请人： Makoto Hanawa ,  Osamu Nishii ,  Susumu Narita ,  Kunio Uchiyama

发明人： Makoto Hanawa ,  Osamu Nishii ,  Susumu Narita ,  Kunio Uchiyama

IPC分类号： G06F9/34 ,  G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3822

摘要： A data processor is provided with a first register storing a first half word of one instruction; a second register storing a second half word of the instruction; a first decoder decoding the first half word and at the same time detecting whether there exists an addressing extension portion between the first half word and the second half word; a second decoder decoding the second half word; and, a decode result generating circuit, to which a detection signal of the first decoder indicates whether the addressing extension portion exists. A decode result of the first decoder and a decode result of the second decoder are supplied to the decode result generating circuit. An extension portion register is provided to store the addressing extension portion. When the first decoder detects the addressing extension portion, the decode result generating circuit invalidates the decode result of the second decoder. On the other hand, in the case where there exists no addressing extension portion, the decode result generating circuit judges, on the basis of the detection signal, that the decode result of the second decoder is valid.

摘要翻译： 数据处理器设置有存储一个指令的前半字的第一寄存器; 存储指令的第二个半字的第二寄存器; 解码所述前半字，并且同时检测在所述前半字和所述第二半字之间是否存在寻址扩展部分的第一解码器; 解码所述第二半字的第二解码器; 以及第一解码器的检测信号指示寻址扩展部分是否存在的解码结果生成电路。 第一解码器的解码结果和第二解码器的解码结果被提供给解码结果生成电路。 提供扩展部分寄存器以存储寻址扩展部分。 当第一解码器检测到寻址扩展部分时，解码结果生成电路使第二解码器的解码结果无效。 另一方面，在不存在寻址扩展部的情况下，解码结果生成电路根据检测信号判断第二解码器的解码结果有效。

公开(公告)号：US20100005324A1

公开(公告)日：2010-01-07

申请号：US12346268

申请日：2008-12-30

申请人： Yonetaro TOTSUKA ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

发明人： Yonetaro TOTSUKA ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

IPC分类号： G06F1/26

CPC分类号： G06F1/3296 ,  G06F1/3203 ,  Y02D10/172 ,  Y02D50/20

摘要： The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.

摘要翻译： 本发明的特征在于：处理器主电路，用于在处理器芯片上执行程序指令串; 衬底偏置切换单元，用于切换施加到处理器主电路的衬底的衬底偏压的电压; 以及操作模式控制单元，用于响应于执行处理器主电路中的待机模式的指令，控制所述衬底偏置切换单元，使得所述偏置切换到所述处理器主电路的电压 待机模式，并且为了响应于来自外部的待机释放的中断来控制衬底偏置切换单元，使得偏置被切换到用于正常模式的电压，并且还用于释放 在切换到其上的偏置电压已经稳定之后，处理器主电路的待机重新开始操作。

公开(公告)号：US06532528B1

公开(公告)日：2003-03-11

申请号：US09563753

申请日：2000-05-01

申请人： Junichi Nishimoto ,  Osamu Nishii ,  Fumio Arakawa ,  Susumu Narita ,  Masayuki Ito ,  Makoto Toda ,  Kunio Uchiyama

发明人： Junichi Nishimoto ,  Osamu Nishii ,  Fumio Arakawa ,  Susumu Narita ,  Masayuki Ito ,  Makoto Toda ,  Kunio Uchiyama

IPC分类号： G06F1210

CPC分类号： G06F12/1027 ,  G06F2212/652

摘要： A data processor in which a speed of an address translating operation is raised is disclosed. A translation lookaside buffer is divided into a buffer for data and a buffer for instruction, address translation information for instruction is also stored into a translation lookaside buffer for data, and when a translation miss occurs in a translation lookaside buffer for instruction, new address translation information is fetched from the translation lookaside buffer for data. A high speed of the address translating operation can be realized as compared with that in case of obtaining address translation information from an external address translation table each time a translation miss occurs in the translation lookaside buffer for instruction.

摘要翻译： 公开了一种提高地址转换操作速度的数据处理器。 翻译后备缓冲区被分为用于数据的缓冲器和用于指令的缓冲器，用于指令的地址转换信息也被存储到用于数据的翻译后备缓冲器中，并且当用于指令的翻译后备缓冲器中发生翻译错误时，新的地址转换 从数据的翻译后备缓冲区中提取信息。 与每次在用于指令的翻译后备缓冲器中发生翻译缺口时从外部地址转换表获得地址转换信息的情况相比，可以实现地址转换操作的高速度。

公开(公告)号：US07958379B2

公开(公告)日：2011-06-07

申请号：US12346268

申请日：2008-12-30

申请人： Yonetaro Totsuka ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

发明人： Yonetaro Totsuka ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F1/32 ,  B23K11/24

CPC分类号： G06F1/3296 ,  G06F1/3203 ,  Y02D10/172 ,  Y02D50/20

摘要： The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.

摘要翻译： 本发明的特征在于：处理器主电路，用于在处理器芯片上执行程序指令串; 衬底偏置切换单元，用于切换施加到处理器主电路的衬底的衬底偏压的电压; 以及操作模式控制单元，用于响应于执行处理器主电路中的待机模式的指令，控制所述衬底偏置切换单元，使得所述偏置切换到所述处理器主电路的电压 待机模式，并且为了响应于来自外部的待机释放的中断来控制衬底偏置切换单元，使得偏置被切换到用于正常模式的电压，并且还用于释放 在切换到其上的偏置电压已经稳定之后，处理器主电路的待机重新开始操作。

公开(公告)号：US08364988B2

公开(公告)日：2013-01-29

申请号：US13101678

申请日：2011-05-05

申请人： Yonetaro Totsuka ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

发明人： Yonetaro Totsuka ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F1/32 ,  G06F11/30 ,  H02J1/00

CPC分类号： G06F1/3296 ,  G06F1/3203 ,  Y02D10/172 ,  Y02D50/20

摘要： The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.

公开(公告)号：US07475261B2

公开(公告)日：2009-01-06

申请号：US10768136

申请日：2004-02-02

申请人： Yonetaro Totsuka ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

发明人： Yonetaro Totsuka ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F1/32

CPC分类号： G06F1/3296 ,  G06F1/3203 ,  Y02D10/172 ,  Y02D50/20

摘要： The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.

摘要翻译： 本发明的特征在于：处理器主电路，用于在处理器芯片上执行程序指令串; 衬底偏置切换单元，用于切换施加到处理器主电路的衬底的衬底偏压的电压; 以及操作模式控制单元，用于响应于执行处理器主电路中的待机模式的指令，控制所述衬底偏置切换单元，使得所述偏置切换到所述处理器主电路的电压 待机模式，并且为了响应于来自外部的待机释放的中断来控制衬底偏置切换单元，使得偏置被切换到用于正常模式的电压，并且还用于释放 在切换到其上的偏置电压已经稳定之后，处理器主电路的待机重新开始操作。

公开(公告)号：US6092172A

公开(公告)日：2000-07-18

申请号：US950668

申请日：1997-10-15

申请人： Junichi Nishimoto ,  Osamu Nishii ,  Fumio Arakawa ,  Susumu Narita ,  Masayuki Ito ,  Makoto Toda ,  Kunio Uchiyama

发明人： Junichi Nishimoto ,  Osamu Nishii ,  Fumio Arakawa ,  Susumu Narita ,  Masayuki Ito ,  Makoto Toda ,  Kunio Uchiyama

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F12/1027 ,  G06F2212/652

摘要： A data processor in which a speed of an address translating operation is raised is disclosed. A translation lookaside buffer is divided into a buffer for data and a buffer for instruction, address translation information for instruction is also stored into a translation lookaside buffer for data, and when a translation miss occurs in a translation lookaside buffer for instruction, new address translation information is fetched from the translation lookaside buffer for data. A high speed of the address translating operation can be realized as compared with that in case of obtaining address translation information from an external address translation table each time a translation miss occurs in the translation lookaside buffer for instruction.

摘要翻译： 公开了一种提高地址转换操作速度的数据处理器。 翻译后备缓冲区被分为用于数据的缓冲器和用于指令的缓冲器，用于指令的地址转换信息也被存储到用于数据的翻译后备缓冲器中，并且当用于指令的翻译后备缓冲器中发生翻译错误时，新的地址转换 从数据的翻译后备缓冲区中提取信息。 与每次在用于指令的翻译后备缓冲器中发生翻译缺口时从外部地址转换表获得地址转换信息的情况相比，可以实现地址转换操作的高速度。

公开(公告)号：US06715090B1

公开(公告)日：2004-03-30

申请号：US09308488

申请日：1999-05-20

申请人： Yonetaro Totsuka ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

发明人： Yonetaro Totsuka ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

IPC分类号： G06F130

CPC分类号： G06F1/3296 ,  G06F1/3203 ,  Y02D10/172 ,  Y02D50/20

摘要： The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.

摘要翻译： 本发明的特征在于：处理器主电路，用于在处理器芯片上执行程序指令串; 衬底偏置切换单元，用于切换施加到处理器主电路的衬底的衬底偏压的电压; 以及操作模式控制单元，用于响应于执行处理器主电路中的待机模式的指令，控制所述衬底偏置切换单元，使得所述偏置切换到所述处理器主电路的电压 待机模式，并且为了响应于来自外部的待机释放的中断来控制衬底偏置切换单元，使得偏置被切换到用于正常模式的电压，并且还用于释放 在切换到其上的偏置电压已经稳定之后，处理器主电路的待机重新开始操作。

公开(公告)号：US5408625A

公开(公告)日：1995-04-18

申请号：US169728

申请日：1993-12-17

申请人： Susumu Narita ,  Fumio Arakawa ,  Tetsuhiko Okada ,  Kunio Uchiyama

发明人： Susumu Narita ,  Fumio Arakawa ,  Tetsuhiko Okada ,  Kunio Uchiyama

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/04 ,  G06F9/00

CPC分类号： G06F9/3822 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/3867

摘要： An instruction fetch unit IU in a microprocessor capable of decoding two instructions in parallel fetches first and second instructions of the shortest instructions in one cycle. The fetched first instruction is supplied to and decoded by a first instruction decoder ID0, while the fetched second instruction is supplied to and decoded by a second instruction decoder ID1. In a case where an instruction having a bit width longer than the shortest instruction has been fetched by the instruction fetch unit IU, information to be decoded by the second instruction decoder ID1 is the non-head code of the instruction, and hence, a pipeline control unit PCNT invalidates the decoded result of the second instruction decoder ID1. Thus, it is permitted to decode the two shortest instructions in parallel, and to eliminate the erroneous information of the decoded result of the second decoder in the case of the fetch of the non-shortest instruction.

摘要翻译： 能够并行解码两个指令的微处理器中的指令获取单元IU在一个周期中获取最短指令的第一和第二指令。 所提取的第一指令被提供给第一指令解码器ID0并由第一指令解码器ID0解码，而所提取的第二指令被提供给第二指令解码器ID1并由第二指令解码器ID1解码。 在指令获取单元IU取得比长度短于最短指令的指令的情况下，由第二指令解码器ID1解码的信息是指令的非头部代码，因此，管线 控制单元PCNT使第二指令解码器ID1的解码结果无效。 因此，允许并行地解码两个最短指令，并且在取得非最短指令的情况下，消除第二解码器的解码结果的错误信息。

公开(公告)号：US5148532A

公开(公告)日：1992-09-15

申请号：US611484

申请日：1990-11-07

申请人： Susumu Narita ,  Makoto Hanawa ,  Tadahiko Nishimukai ,  Tetsuhiko Okada

发明人： Susumu Narita ,  Makoto Hanawa ,  Tadahiko Nishimukai ,  Tetsuhiko Okada

IPC分类号： G06F9/26

CPC分类号： G06F9/264

摘要： In a pipeline processing microprocessor, an instruction fetch unit is keyed to the formation or nonformation of a conditional branch micro-instruction result to determine the subsequent macro-instruction to be fetched from an external memory or cache. A macro-instruction is first decoded in an instruction decoder to generate micro-addresses which address is a micro-ROM. The first micro-instruction retrieved from the micro-ROM contains information for executing a conditional discrimination, a signal requesting branch ready, and a subsequent micro-address for the actual execution of the branch request in accordance with the result of the conditional discrimination. When the branch condition is satisfied, a micro-address generating circuit feeds the subsequent micro-instruction to a micro-ROM address decoder and the least significant bit of the subsequent micro-address to a micro-address analyzing circuit. The branch ready information of the first micro-instruction is also fed to the micro-address analyzing circuit to prefetch a target branch macro-instruction from an associated memory before the micro-ROM outputs the micro-instruction, corresponding to the subsequent micro-address, to the instruction execution unit, in effect bypassing the delay associated with micro-ROM decoding.