摘要:
A clock signal duty correction circuit includes: a first transition timing control unit configured to generate a first control signal for controlling a rising timing of a duty correction clock signal by using a clock signal; a second transition timing control unit configured to generate a second control signal for varying a falling timing of the duty correction clock signal by using the clock signal according to a code signal; and a differential buffer unit configured to generate the duty correction clock signal, whose rising time or falling time is adjusted, in response to the first control signal and the second control signal.
摘要:
A power control circuit includes a check unit that receives a reference clock and generates a check signal for cyclically activating a feedback loop of a DLL circuit, a phase detecting unit that detects a phase difference between the reference clock and a feedback clock, and generates a phase difference detection signal, and a signal combining unit that generates a power cutoff signal in response to a locking completion signal, the check signal, and the phase difference detection signal.
摘要:
A semiconductor integrated circuit is provided. The semiconductor integrated circuit includes: a delay locked loop (DLL) output block configured to delay an input clock signal by a predetermined time in response to a plurality of delay control signals and provide a DLL clock signal; a locking control block configured to compare a phase of a reference clock signal and a phase of a feedback clock signal, and synchronize the phase of the reference clock signal and the phase of the feedback clock signal in response to the plurality of delay control signals; and a locking detection block configured to detect whether the phase of the reference clock signal and the phase of the feedback clock signal are synchronized and the DLL clock signal is locked, wherein, when the DLL clock signal is locked, the locking control block provides the reference clock signal, which is obtained by dividing the input clock signal by n (where n is a natural number equal to or greater than 2), as an internal DLL clock signal.
摘要:
A semiconductor integrated circuit is disclosed. The disclosed semiconductor integrated circuit of the present invention includes a DLL (Delay Locked Loop) controller that controls whether to activate a DLL at the entry of a power down mode, in response to a result of detecting whether a range of phase change of an external clock signal is within a predetermined range, and a DLL block that provides a result of comparing a reference clock signal with a feedback clock signal to the DLL controller and also provides a delay locked clock signal that is periodically updated, in response to the reference clock signal, under the control of an activated output signal from the DLL controller.
摘要:
A clock receiver in a semiconductor integrated circuit includes a first clock buffer configured to buffer an external clock to generate a low frequency buffered clock in response to a first operation signal; a second clock buffer configured to buffer the external clock to generate a high frequency buffered clock in response to a second operation signal; and an internal clock generating unit configured to receive the low frequency buffered clock and the high frequency buffered clock, to control states of the first operation signal and the second operation signal and to generate an internal clock.
摘要:
A delay locked loop (DLL) apparatus includes a first delay unit converting a reference clock into a rising clock. A second delay unit converts the reference clock into a falling clock, and a replica delay unit replica-delays the rising clock. A first phase detector compares the phases of the reference clock and the delayed rising clock to output a first detection signal corresponding to the compared phases. A controller synchronizes the rising edge of the rising clock with the rising edge of the reference clock according to the first detection signal of the first phase detector. A second phase detector compares the phases of the synchronized rising clock and the synchronization clock to output a second detection signal corresponding to the compared phases. The DLL apparatus compensates for a skew between an external clock and data and between external and internal clocks by employing a single replica delay unit.
摘要:
A phase synchronization apparatus includes a bias control unit configured to sequentially delay an input clock signal to generate bias control signals having multiple bits, a bias generation unit configured to generate a pull-up bias voltage having a level that corresponds to logical values of the bias control signals, and to generate a pull-down bias voltage in response to a control signal; and a voltage controlled oscillator configured to include a plurality of delay cells respectively having a pull-up terminal and a pull-down terminal to generate an output clock signal in response to the control voltage, wherein the pull-up bias voltage is supplied to the pull-up terminals of the respective delay cells and the pull-down bias voltage is supplied to the pull-down terminals of the respective delay cells.
摘要:
A duty cycle correcting circuit includes a duty ratio control signal generating block that detects a duty ratio of input clock signals and generates a duty ratio control signal comprising a plurality of bits, a power supply block that supplies a voltage to output nodes, and a signal processing block that controls voltage levels of the output nodes to correspond to voltage levels of the input clock signals in response to the plurality of bits of duty ratio control signals.
摘要:
A DLL circuit includes a duty ratio detection unit that detects a duty ratio of a rising clock and a duty ratio of a falling clock, thereby outputting a duty ratio detection signal. A correction control unit generates a correction control signal in response to the duty ratio detection signal. A duty ratio correction unit corrects a duty ratio of an internal. clock in response to the correction control signal, thereby outputting a reference clock.
摘要:
Various embodiments of a semiconductor integrated circuit. According to one exemplary embodiment, a semiconductor integrated circuit includes a multi-phase clock generator that is configured to generate a multi-phase internal clock; a first edge combining unit that is configured to generate a first output clock having a first frequency by combining rising edges of clocks included in the internal clock, and transmit the first output clock to a first port; and a second edge combining unit that is configured to generate a second output clock having a second frequency by combining rising edges of clocks included in the internal clock, and transmit the output clock to a second port.