Semiconductor apparatus and calibration method thereof
    1.
    发明授权
    Semiconductor apparatus and calibration method thereof 有权
    半导体装置及其校正方法

    公开(公告)号:US08154019B2

    公开(公告)日:2012-04-10

    申请号:US12649193

    申请日:2009-12-29

    IPC分类号: H01L23/58

    摘要: A semiconductor apparatus includes a reference voltage generation unit, a comparison voltage generation unit, and a calibration unit. The reference voltage generation unit is disposed in a reference die and configured to generate a reference voltage. The comparison voltage generation unit is disposed in a die stacked on the reference die and configured to generate a comparison voltage in response to a calibration control signal. The calibration unit is configured to compare a level of the reference voltage with a level of the comparison voltage and generate the calibration control signal.

    摘要翻译: 半导体装置包括参考电压产生单元,比较电压产生单元和校准单元。 参考电压产生单元设置在参考管芯中,并被配置为产生参考电压。 比较电压产生单元设置在堆叠在参考管芯上的管芯中,并被配置为响应校准控制信号产生比较电压。 校准单元被配置为将参考电压的电平与比较电压的电平进行比较并产生校准控制信号。

    SEMICONDUCTOR APPARATUS AND CALIBRATION METHOD THEREOF
    2.
    发明申请
    SEMICONDUCTOR APPARATUS AND CALIBRATION METHOD THEREOF 有权
    半导体器件及其校准方法

    公开(公告)号:US20110074369A1

    公开(公告)日:2011-03-31

    申请号:US12649193

    申请日:2009-12-29

    IPC分类号: G05F1/00 H01L23/58

    摘要: A semiconductor apparatus includes a reference voltage generation unit, a comparison voltage generation unit, and a calibration unit. The reference voltage generation unit is disposed in a reference die and configured to generate a reference voltage. The comparison voltage generation unit is disposed in a die stacked on the reference die and configured to generate a comparison voltage in response to a calibration control signal. The calibration unit is configured to compare a level of the reference voltage with a level of the comparison voltage and generate the calibration control signal.

    摘要翻译: 半导体装置包括参考电压产生单元,比较电压产生单元和校准单元。 参考电压产生单元设置在参考管芯中,并被配置为产生参考电压。 比较电压产生单元设置在堆叠在参考管芯上的管芯中,并被配置为响应校准控制信号产生比较电压。 校准单元被配置为将参考电压的电平与比较电压的电平进行比较并产生校准控制信号。

    Data line termination circuit
    3.
    发明授权
    Data line termination circuit 有权
    数据线终端电路

    公开(公告)号:US08330486B2

    公开(公告)日:2012-12-11

    申请号:US12956416

    申请日:2010-11-30

    IPC分类号: H03K17/16

    摘要: A data line termination circuit includes a swing-width sensing unit configured to sense a swing width of a voltage of a data line and output a sensed signal, and a variable termination unit configured to adjust a termination resistance value of the data line in response to the sensed signal. The swing-width sensing unit can sense if the swing width is less than or greater than a predetermined swing width, and the swing width of the voltage of the data line can be reduced or increased to maintain the voltage of the data line within a predetermined range.

    摘要翻译: 数据线终端电路包括:摆动宽度检测单元,被配置为感测数据线的电压的摆幅并输出感测信号;以及可变终端单元,被配置为响应于所述数据线的终端电阻值 感测信号。 摆幅感测单元可以感测摆动宽度是否小于或大于预定的摆动宽度,并且可以减小或增加数据线的电压的摆动宽度,以将数据线的电压保持在预定的 范围。

    Semiconductor apparatus
    4.
    发明授权
    Semiconductor apparatus 有权
    半导体装置

    公开(公告)号:US08618541B2

    公开(公告)日:2013-12-31

    申请号:US13341299

    申请日:2011-12-30

    IPC分类号: H01L23/58 G11C29/00

    摘要: A semiconductor apparatus includes first and second vias, a first circuit unit, a second circuit unit and a third circuit unit. The first and second vias electrically connect a first chip and a second chip with each other. The first circuit unit is disposed in the first chip, receives test data, and is connected with the first via. The second circuit unit is disposed in the first chip, and is connected with the second via and the first circuit unit. The third circuit unit is disposed in the second chip, and is connected with the first via. The first circuit unit outputs an output signal thereof to one of the first via and the second circuit unit in response to a first control signal.

    摘要翻译: 半导体装置包括第一和第二通孔,第一电路单元,第二电路单元和第三电路单元。 第一和第二通孔将第一芯片和第二芯片彼此电连接。 第一电路单元设置在第一芯片中,接收测试数据,并与第一通孔连接。 第二电路单元设置在第一芯片中,并与第二通孔和第一电路单元连接。 第三电路单元设置在第二芯片中,并与第一通孔连接。 第一电路单元响应于第一控制信号将其输出信号输出到第一通孔和第二电路单元之一。

    Data line termination circuit
    5.
    发明授权
    Data line termination circuit 失效
    数据线终端电路

    公开(公告)号:US07863928B2

    公开(公告)日:2011-01-04

    申请号:US12403549

    申请日:2009-03-13

    IPC分类号: H03K17/16

    摘要: A data line termination circuit includes a swing-width sensing unit configured to sense a swing width of a voltage of a data line and output a sensed signal, and a variable termination unit configured to adjust a termination resistance value of the data line in response to the sensed signal. The swing-width sensing unit can sense if the swing width is less than or greater than a predetermined swing width, and the swing width of the voltage of the data line can be reduced or increased to maintain the voltage of the data line within a predetermined range.

    摘要翻译: 数据线终端电路包括:摆动宽度检测单元,被配置为感测数据线的电压的摆幅并输出感测信号;以及可变终端单元,被配置为响应于所述数据线的终端电阻值 感测信号。 摆幅感测单元可以感测摆动宽度是否小于或大于预定的摆动宽度,并且可以减小或增加数据线的电压的摆动宽度,以将数据线的电压保持在预定的 范围。

    SIP semiconductor system
    7.
    发明授权
    SIP semiconductor system 有权
    SIP半导体系统

    公开(公告)号:US08811101B2

    公开(公告)日:2014-08-19

    申请号:US13399643

    申请日:2012-02-17

    IPC分类号: G11C7/00 G11C29/00

    CPC分类号: G11C29/48 G11C2029/0401

    摘要: A system in package (SIP) semiconductor system includes a memory device, a controller, a first input/output terminal, a test control unit, and a second input/output terminal. The controller communicates with the memory device. The first input/output terminal performs communication between the controller and a device external to the SIP semiconductor system. The test control unit controls a predetermined test mode of the memory device. The second input/output terminal performs communication between the test control unit and at least the device external to the SIP semiconductor system.

    摘要翻译: 封装(SIP)半导体系统包括存储器件,控制器,第一输入/输出端子,测试控制单元和第二输入/输出端子。 控制器与存储器件通信。 第一输入/输出端子执行控制器与SIP半导体系统外部的设备之间的通信。 测试控制单元控制存储器件的预定测试模式。 第二输入/输出端子执行测试控制单元与至少在SIP半导体系统外部的设备之间的通信。

    CIRCUIT FOR GENERATING INTERNAL VOLTAGE OF SEMINCONDUCTOR MEMORY APPARATUS
    8.
    发明申请
    CIRCUIT FOR GENERATING INTERNAL VOLTAGE OF SEMINCONDUCTOR MEMORY APPARATUS 审中-公开
    用于产生电导率存储器内部电压的电路

    公开(公告)号:US20100039093A1

    公开(公告)日:2010-02-18

    申请号:US12480951

    申请日:2009-06-09

    IPC分类号: H03H1/00

    CPC分类号: G11C5/147

    摘要: An internal voltage generating circuit of a semiconductor memory apparatus includes a control signal generating unit configured to enable one of a plurality of control signals in response to a calibration code; and a signal variable voltage distributing unit configured to determine a distribution ratio in response to one enabled control signal of the plurality of control signals and generate an internal voltage by distributing an external voltage at the determined distribution ratio.

    摘要翻译: 半导体存储装置的内部电压产生电路包括:控制信号生成单元,被配置为响应于校准码启用多个控制信号中的一个; 以及信号可变电压分配单元,被配置为响应于所述多个控制信号的一个使能控制信号来确定分配比,并且通过以所确定的分配比分配外部电压来产生内部电压。

    SEMICONDUCTOR MEMORY APPARATUS AND TEST METHOD THEREOF
    9.
    发明申请
    SEMICONDUCTOR MEMORY APPARATUS AND TEST METHOD THEREOF 有权
    半导体存储器及其测试方法

    公开(公告)号:US20120057413A1

    公开(公告)日:2012-03-08

    申请号:US12948874

    申请日:2010-11-18

    摘要: A semiconductor memory apparatus includes a clock control unit configured to receive a first clock when an enable signal is activated and generate a second clock which has a cycle closer in length to a target clock cycle than the first clock; a DLL input clock generation unit configured to output one of the first clock and the second clock as a DLL input clock according to a DLL select signal; and an address/command input clock generation unit configured to output one of the first clock and the second clock as an AC input clock according to the enable signal.

    摘要翻译: 一种半导体存储装置,包括:时钟控制单元,被配置为当使能信号被激活时接收第一时钟,并产生具有与第一时钟相对于目标时钟周期更长的周期的第二时钟; DLL输入时钟生成单元,被配置为根据DLL选择信号将第一时钟和第二时钟中的一个作为DLL输入时钟输出; 以及地址/命令输入时钟生成单元,被配置为根据使能信号将第一时钟和第二时钟中的一个作为AC输入时钟输出。

    SEMICONDUCTOR INTEGRATED CIRCUIT
    10.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
    半导体集成电路

    公开(公告)号:US20090046528A1

    公开(公告)日:2009-02-19

    申请号:US12018732

    申请日:2008-01-23

    申请人: Hyung Dong Lee

    发明人: Hyung Dong Lee

    IPC分类号: G11C7/08

    摘要: A semiconductor integrated circuit includes a sense amplifier for sensing input data and a sense amplifier controller for blocking a signal path between the sense amplifier and a memory cell when a test mode signal is activated.

    摘要翻译: 半导体集成电路包括用于感测输入数据的读出放大器和用于在测试模式信号被激活时阻塞读出放大器与存储单元之间的信号路径的读出放大器控制器。