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公开(公告)号：US20100177554A1
公开(公告)日：2010-07-15
申请号：US12502211
申请日：2009-07-13
申请人： Yong Lu , Hongyue Liu , Maroun Khoury , Yiran Chen
发明人： Yong Lu , Hongyue Liu , Maroun Khoury , Yiran Chen
CPC分类号： G11C13/0004 , G11C11/16 , G11C11/1659 , G11C11/1675 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C2213/76
摘要： A resistive sense memory apparatus includes a bipolar select device having a semiconductor substrate and a plurality of transistors disposed in the semiconductor substrate and forming a row or transistors. Each transistor includes an emitter contact and a collector contact. Each collector contact is electrically isolated from each other and each emitter contact is electrically isolated from each other. A gate contact extends along a channel region between the emitter contact and a collector contact. A base contact is disposed within the semiconductor substrate such that the emitter contact and a collector contact is between the gate contact and the base contact. A resistive sense memory cells is electrically coupled to each collector contact or emitter contact and a bit line.
摘要翻译： 电阻式感测存储装置包括具有半导体衬底和设置在半导体衬底中并形成行或晶体管的多个晶体管的双极选择器件。 每个晶体管包括发射极触点和集电极触点。 每个集电极触点彼此电隔离，并且每个发射极触点彼此电隔离。 栅极触点沿发射极触点和集电极触点之间的沟道区域延伸。 基极触点设置在半导体衬底内，使得发射极触点和集电极触点位于栅极触点和基极触点之间。 电阻读出存储单元电耦合到每个集电极触点或发射极触点和位线。
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公开(公告)号：US09030867B2
公开(公告)日：2015-05-12
申请号：US12502211
申请日：2009-07-13
申请人： Yong Lu , Hongyue Liu , Maroun Khoury , Yiran Chen
发明人： Yong Lu , Hongyue Liu , Maroun Khoury , Yiran Chen
CPC分类号： G11C13/0004 , G11C11/16 , G11C11/1659 , G11C11/1675 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C2213/76
摘要： A resistive sense memory apparatus includes a bipolar select device having a semiconductor substrate and a plurality of transistors disposed in the semiconductor substrate and forming a row or transistors. Each transistor includes an emitter contact and a collector contact. Each collector contact is electrically isolated from each other and each emitter contact is electrically isolated from each other. A gate contact extends along a channel region between the emitter contact and a collector contact. A base contact is disposed within the semiconductor substrate such that the emitter contact and a collector contact is between the gate contact and the base contact. A resistive sense memory cells is electrically coupled to each collector contact or emitter contact and a bit line.
摘要翻译： 电阻式感测存储装置包括具有半导体衬底和设置在半导体衬底中并形成行或晶体管的多个晶体管的双极选择器件。 每个晶体管包括发射极触点和集电极触点。 每个集电极触点彼此电隔离，并且每个发射极触点彼此电隔离。 栅极触点沿发射极触点和集电极触点之间的沟道区域延伸。 基极触点设置在半导体衬底内，使得发射极触点和集电极触点位于栅极触点和基极触点之间。 电阻读出存储单元电耦合到每个集电极触点或发射极触点和位线。
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公开(公告)号：US20130003448A1
公开(公告)日：2013-01-03
申请号：US13611225
申请日：2012-09-12
申请人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
发明人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G11C11/1659
摘要： A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. The memory unit is configured to be precharged to a specified precharge voltage level and the precharge voltage is less than a threshold voltage of the first diode and second diode.
摘要翻译： 存储单元包括磁性隧道结数据单元电耦合到位线和源极线。 磁隧道结数据单元被配置为通过使写入电流通过磁性隧道结数据单元而在高电阻状态和低电阻状态之间切换。 第一二极管电磁性地在磁性隧道结数据单元和源极线之间，第二个二极管电气地在磁性隧道结数据单元和源极线之间。 第一二极管和第二二极管并联电连接并具有相反的正向偏压方向。 存储器单元被配置为预充电到指定的预充电电压电平，并且预充电电压小于第一二极管和第二二极管的阈值电压。
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公开(公告)号：US08289746B2
公开(公告)日：2012-10-16
申请号：US12948824
申请日：2010-11-18
申请人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
发明人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
CPC分类号： G11C11/1675 , G11C11/1659
摘要： A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. The memory unit is configured to be precharged to a specified precharge voltage level and the precharge voltage is less than a threshold voltage of the first diode and second diode.
摘要翻译： 存储单元包括磁性隧道结数据单元电耦合到位线和源极线。 磁隧道结数据单元被配置为通过使写入电流通过磁性隧道结数据单元而在高电阻状态和低电阻状态之间切换。 第一二极管电磁性地在磁性隧道结数据单元和源极线之间，第二个二极管电气地在磁性隧道结数据单元和源极线之间。 第一二极管和第二二极管并联电连接并具有相反的正向偏压方向。 存储器单元被配置为预充电到指定的预充电电压电平，并且预充电电压小于第一二极管和第二二极管的阈值电压。
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公开(公告)号：US08054675B2
公开(公告)日：2011-11-08
申请号：US13028246
申请日：2011-02-16
申请人： Haiwen Xi , Hongyue Liu , Xiaobin Wang , Yong Lu , Yiran Chen , Yuankai Zheng , Dimitar V. Dimitrov , Dexin Wang , Hai Li
发明人： Haiwen Xi , Hongyue Liu , Xiaobin Wang , Yong Lu , Yiran Chen , Yuankai Zheng , Dimitar V. Dimitrov , Dexin Wang , Hai Li
CPC分类号： G11C11/16 , G11C13/0007 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0057
摘要： Variable write and read methods for resistance random access memory (RRAM) are disclosed. The methods include initializing a write sequence and verifying the resistance state of the RRAM cell. If a write pulse is needed, then two or more write pulses are applied through the RRAM cell to write the desired data state to the RRAM cell. Each subsequent write pulse has substantially the same or greater write pulse duration. Subsequent write pulses are applied to the RRAM cell until the RRAM cell is in the desired data state or until a predetermined number of write pulses have been applied to the RRAM cell. A read method is also disclosed where subsequent read pulses are applied through the RRAM cell until the read is successful or until a predetermined number of read pulses have been applied to the RRAM cell.
摘要翻译： 公开了用于电阻随机存取存储器（RRAM）的可变写和读方法。 这些方法包括初始化写入序列并验证RRAM单元的电阻状态。 如果需要写入脉冲，则通过RRAM单元施加两个或更多写入脉冲，以将期望的数据状态写入RRAM单元。 每个后续写入脉冲具有基本上相同或更大的写入脉冲持续时间。 随后的写入脉冲被施加到RRAM单元，直到RRAM单元处于期望的数据状态，或直到预定数量的写入脉冲已经被施加到RRAM单元为止。 还公开了一种读取方法，其中随后的读取脉冲通过RRAM单元被施加，直到读取成功或直到预定数量的读取脉冲已经被应用于RRAM单元为止。
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公开(公告)号：US08514605B2
公开(公告)日：2013-08-20
申请号：US13611225
申请日：2012-09-12
申请人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
发明人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
CPC分类号： G11C11/1675 , G11C11/1659
摘要： A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. The memory unit is configured to be precharged to a specified precharge voltage level and the precharge voltage is less than a threshold voltage of the first diode and second diode.
摘要翻译： 存储单元包括磁性隧道结数据单元电耦合到位线和源极线。 磁隧道结数据单元被配置为通过使写入电流通过磁性隧道结数据单元而在高电阻状态和低电阻状态之间切换。 第一二极管电磁性地在磁性隧道结数据单元和源极线之间，第二个二极管电气地在磁性隧道结数据单元和源极线之间。 第一二极管和第二二极管并联电连接并具有相反的正向偏压方向。 存储器单元被配置为预充电到指定的预充电电压电平，并且预充电电压小于第一二极管和第二二极管的阈值电压。
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7.发明授权公开(公告)号：US08296620B2
公开(公告)日：2012-10-23
申请号：US12198516
申请日：2008-08-26
申请人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
发明人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
IPC分类号： G06F11/00
CPC分类号： G06F11/1048 , G11C2029/0411
摘要： A method of utilizing at least one block of data, wherein the at least one block of data includes a plurality of cells for storing data and at least one error flag bit, the method including: scanning the block of data for errors; determining the error rate of the block of data; and applying an error correction code to data being read from or written to a cell within the at least one block of data, wherein the error correction code is applied based on the error rate, wherein a weak error correction code is applied when the error rate is below an error threshold, and a strong error correction code is applied when the error rate is at or above the error threshold.
摘要翻译： 一种使用至少一个数据块的方法，其中所述至少一个数据块包括用于存储数据的多个单元和至少一个误差标志位，所述方法包括：扫描所述数据块的错误; 确定数据块的错误率; 以及对所述至少一个数据块中的单元读取或写入的数据应用纠错码，其中，基于所述错误率应用所述纠错码，其中当所述错误率 低于错误阈值，并且当错误率处于或高于错误阈值时应用强纠错码。
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公开(公告)号：US07936588B2
公开(公告)日：2011-05-03
申请号：US12789691
申请日：2010-05-28
申请人： Hongyue Liu , Yong Lu , Andrew Carter , Yiran Chen , Hai Li
发明人： Hongyue Liu , Yong Lu , Andrew Carter , Yiran Chen , Hai Li
IPC分类号： G11C11/00
CPC分类号： G11C7/14 , G11C11/1673
摘要： The present disclosure relates to memory arrays with read reference voltage cells. In particular the present disclosure relates to variable resistive memory cell apparatus and arrays that include a high resistance state reference memory cell and a low resistance state reference memory cell that provides a reliable average reference voltage on chip to compare to a read voltage of a selected memory cell and determine if the selected memory cell is in the high resistance state or low resistance state. These memory arrays are particularly suitable for use with spin-transfer torque memory cells and resolves many systematic issues related to generation of a reliable reference voltage.
摘要翻译： 本公开涉及具有读取参考电压单元的存储器阵列。 特别地，本公开涉及包括高电阻状态参考存储单元和低电阻状态参考存储单元的可变电阻存储单元设备和阵列，其提供片上可靠的平均参考电压以与所选择的存储器的读取电压进行比较 并确定所选存储单元是处于高电阻状态还是低电阻状态。 这些存储器阵列特别适用于自旋转移转矩存储单元，并且解决了与生成可靠参考电压有关的许多系统问题。
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公开(公告)号：US07755923B2
公开(公告)日：2010-07-13
申请号：US12212798
申请日：2008-09-18
申请人： Hongyue Liu , Yong Lu , Andrew Carter , Yiran Chen , Hai Li
发明人： Hongyue Liu , Yong Lu , Andrew Carter , Yiran Chen , Hai Li
IPC分类号： G11C11/00
CPC分类号： G11C7/14 , G11C11/1673
摘要： The present disclosure relates to memory arrays with read reference voltage cells. In particular the present disclosure relates to variable resistive memory cell apparatus and arrays that include a high resistance state reference memory cell and a low resistance state reference memory cell that provides a reliable average reference voltage on chip to compare to a read voltage of a selected memory cell and determine if the selected memory cell is in the high resistance state or low resistance state. These memory arrays are particularly suitable for use with spin-transfer torque memory cells and resolves many systematic issues related to generation of a reliable reference voltage.
摘要翻译： 本公开涉及具有读取参考电压单元的存储器阵列。 特别地，本公开涉及包括高电阻状态参考存储单元和低电阻状态参考存储单元的可变电阻存储单元设备和阵列，其提供片上可靠的平均参考电压以与所选择的存储器的读取电压进行比较 并确定所选存储单元是处于高电阻状态还是低电阻状态。 这些存储器阵列特别适用于自旋转移转矩存储单元，并且解决了与生成可靠参考电压有关的许多系统问题。
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公开(公告)号：US20100091562A1
公开(公告)日：2010-04-15
申请号：US12250036
申请日：2008-10-13
申请人： Yiran Chen , Hai Li , Hongyue Liu , Henry F. Huang , Yong Lu
发明人： Yiran Chen , Hai Li , Hongyue Liu , Henry F. Huang , Yong Lu
CPC分类号： G11C7/04 , G11C11/1659 , G11C11/1673
摘要： A memory device that includes at least one memory cell, the memory cell includes: a magnetic tunnel junction (MTJ); and a transistor, wherein the transistor is operatively coupled to the MTJ; a bit line; a source line; and a word line, wherein the memory cell is operatively coupled between the bit line and the source line, and the word line is operatively coupled to the transistor; a temperature sensor; and control circuitry, wherein the temperature sensor is operatively coupled to the control circuitry and the control circuitry and temperature sensor are configured to control a current across the memory cell.
摘要翻译： 一种包括至少一个存储单元的存储器件，所述存储单元包括：磁性隧道结（MTJ）; 和晶体管，其中所述晶体管可操作地耦合到所述MTJ; 有点线 源线; 和字线，其中所述存储器单元可操作地耦合在所述位线和所述源极线之间，并且所述字线可操作地耦合到所述晶体管; 温度传感器; 以及控制电路，其中所述温度传感器可操作地耦合到所述控制电路，并且所述控制电路和温度传感器被配置为控制横跨所述存储器单元的电流。
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