公开(公告)号：US20080084779A1

公开(公告)日：2008-04-10

申请号：US11565016

申请日：2006-11-30

申请人： Yong-Taek Jeong ,  Sang-Chul Kang

发明人： Yong-Taek Jeong ,  Sang-Chul Kang

IPC分类号： G11C5/14 ,  G11C8/00

CPC分类号： G11C16/12 ,  G11C5/145

摘要： A semiconductor device includes a memory cell array and a command interface that is configured to receive a command from outside of the semiconductor memory device. The command interface is further configured to interpret the received command and to determine if the received command is a continuous operation command. The command interface outputs a command signal corresponding to the command and at least one flag signal that indicates a continuous operation section if the command is a continuous operation command. A control unit is configured to receive the command signal and the at least one flag signal output from the command interface, and to generate a pump control signal based on the received command signal and the at least one flag signal. A charge pump is configured to generate a voltage in response to the pump control signal for use in accessing the memory cell array to read right and/or erase data.

摘要翻译： 半导体器件包括存储单元阵列和配置为从半导体存储器件的外部接收命令的命令接口。 命令接口还被配置为解释所接收的命令并且确定所接收的命令是否是连续的操作命令。 如果命令是连续操作命令，则命令接口输出对应于命令的命令信号和至少一个指示连续操作部分的标志信号。 控制单元被配置为接收从命令接口输出的命令信号和至少一个标志信号，并且基于接收的命令信号和至少一个标志信号产生泵控制信号。 电荷泵被配置为响应于泵控制信号产生电压，以用于访问存储单元阵列以读取和/或擦除数据。

公开(公告)号：US07894258B2

公开(公告)日：2011-02-22

申请号：US12188057

申请日：2008-08-07

申请人： Yong-Taek Jeong ,  Sang-Chul Kang ,  Kyong-Ae Kim

发明人： Yong-Taek Jeong ,  Sang-Chul Kang ,  Kyong-Ae Kim

IPC分类号： G11C11/34

CPC分类号： G11C11/5621 ,  G11C7/1006 ,  G11C16/3454 ,  G11C2211/5646

摘要： A flash memory device capable of efficiently determining whether most significant bit (MSB) programming has been performed is provided. The flash memory device includes a cell array, a control unit, and a determination unit. The cell array includes at least one flag cell for storing information about whether MSB programming has been performed on a multi-level cell. The control unit controls a program operation, a read operation, and an erasure operation with respect to the cell array. The determination unit receives flag data stored in the flag cells, performs an OR operation and/or an AND operation on the flag data, and generates a determination signal based on a result of the OR operation and/or the AND operation, wherein the determination signal represents whether the MSB programming has been performed.

摘要翻译： 提供能够有效地确定是否执行最高有效位（MSB）编程的快闪存储器件。 闪存器件包括单元阵列，控制单元和确定单元。 单元阵列包括至少一个标志单元，用于存储关于是否在多级单元上执行了MSB编程的信息。 控制单元控制关于单元阵列的程序操作，读取操作和擦除操作。 确定单元接收存储在标志单元中的标志数据，对标志数据执行“或”运算和/或“与”运算，并且基于“或”运算和/或“与”运算的结果生成确定信号，其中确定 信号表示是否已经执行了MSB编程。

公开(公告)号：US20080068886A1

公开(公告)日：2008-03-20

申请号：US11843902

申请日：2007-08-23

申请人： Sang Chul Kang ,  Yong-Taek Jeong

发明人： Sang Chul Kang ,  Yong-Taek Jeong

IPC分类号： G11C16/06

CPC分类号： G11C16/102 ,  G11C11/5628 ,  G11C16/3418

摘要： Methods of executing a multi-page copyback program in a non-volatile memory device are provided, where the non-volatile memory device includes a memory having a plurality of memory blocks. A page of data of the memory block having a first address is replaced responsive to a generated multi-page copyback program command. It is determined if the first address of the page of data is the same as a stored address of the page at which the failure was detected. The first address is incremented if it is determined that the first address and the stored address are not the same. The pages of data are replaced, the addressed are compared and the addresses are incremented until it is determined that the incremented address and the stored address are the same. Related devices and systems are also provided herein.

摘要翻译： 提供了在非易失性存储器件中执行多页复印程序的方法，其中非易失性存储器件包括具有多个存储器块的存储器。 具有第一地址的存储块的数据页被响应于所生成的多页复印程序命令而被替换。 确定数据页面的第一个地址是否与检测到故障的页面的存储地址相同。 如果确定第一个地址和存储的地址不相同，则第一个地址递增。 替换数据页面，比较寻址的地址，并增加地址，直到确定增加的地址和存储的地址相同。 本文还提供了相关设备和系统。

公开(公告)号：US07684241B2

公开(公告)日：2010-03-23

申请号：US11843902

申请日：2007-08-23

申请人： Sang-Chul Kang ,  Yong-Taek Jeong

发明人： Sang-Chul Kang ,  Yong-Taek Jeong

IPC分类号： G11C16/06

CPC分类号： G11C16/102 ,  G11C11/5628 ,  G11C16/3418

摘要： Methods of executing a multi-page copyback program in a non-volatile memory device are provided, where the non-volatile memory device includes a memory having a plurality of memory blocks. A page of data of the memory block having a first address is replaced responsive to a generated multi-page copyback program command. It is determined if the first address of the page of data is the same as a stored address of the page at which the failure was detected. The first address is incremented if it is determined that the first address and the stored address are not the same. The pages of data are replaced, the addressed are compared and the addresses are incremented until it is determined that the incremented address and the stored address are the same. Related devices and systems are also provided herein.

摘要翻译： 提供了在非易失性存储器件中执行多页复印程序的方法，其中非易失性存储器件包括具有多个存储器块的存储器。 具有第一地址的存储块的数据页被响应于所生成的多页复印程序命令而被替换。 确定数据页面的第一个地址是否与检测到故障的页面的存储地址相同。 如果确定第一个地址和存储的地址不相同，则第一个地址递增。 替换数据页面，比较寻址的地址，并增加地址，直到确定增加的地址和存储的地址相同。 本文还提供了相关设备和系统。

公开(公告)号：US07508730B2

公开(公告)日：2009-03-24

申请号：US11565016

申请日：2006-11-30

申请人： Yong-Taek Jeong ,  Sang-Chul Kang

发明人： Yong-Taek Jeong ,  Sang-Chul Kang

IPC分类号： G11C8/00

CPC分类号： G11C16/12 ,  G11C5/145

摘要： A semiconductor device includes a memory cell array and a command interface that is configured to receive a command from outside of the semiconductor memory device. The command interface is further configured to interpret the received command and to determine if the received command is a continuous operation command. The command interface outputs a command signal corresponding to the command and at least one flag signal that indicates a continuous operation section if the command is a continuous operation command. A control unit is configured to receive the command signal and the at least one flag signal output from the command interface, and to generate a pump control signal based on the received command signal and the at least one flag signal. A charge pump is configured to generate a voltage in response to the pump control signal for use in accessing the memory cell array to read write and/or erase data.

摘要翻译： 半导体器件包括存储单元阵列和配置为从半导体存储器件的外部接收命令的命令接口。 命令接口还被配置为解释所接收的命令并且确定所接收的命令是否是连续的操作命令。 如果命令是连续操作命令，则命令接口输出对应于命令的命令信号和至少一个指示连续操作部分的标志信号。 控制单元被配置为接收从命令接口输出的命令信号和至少一个标志信号，并且基于接收的命令信号和至少一个标志信号产生泵控制信号。 电荷泵被配置为响应于泵控制信号产生电压，以用于访问存储器单元阵列以读取写入和/或擦除数据。

公开(公告)号：US20070268774A1

公开(公告)日：2007-11-22

申请号：US11634061

申请日：2006-12-06

申请人： Jong-Hoon Lee ,  Yong-Taek Jeong ,  Jin-Kook Kim

发明人： Jong-Hoon Lee ,  Yong-Taek Jeong ,  Jin-Kook Kim

IPC分类号： G11C8/00 ,  G11C11/34 ,  G11C16/06

CPC分类号： G11C8/08 ,  G11C11/419 ,  G11C16/08 ,  G11C16/12

摘要： Embodiments of the invention provide a high voltage transfer circuit, a row decoder circuit comprising the high voltage transfer circuit, and a non-volatile semiconductor memory device comprising the high voltage transfer circuit. In one embodiment, the invention provides a high voltage transfer circuit of a semiconductor memory device comprising a high voltage switch comprising a high voltage transistor comprising a first terminal connected to a boosted voltage via a first depletion-type transistor and comprising a second terminal connected to an output node via a second depletion-type transistor. The high voltage transfer circuit further comprises a driver circuit adapted to drive the first and second depletion-type transistors and the high voltage transistor in response to an input signal.

摘要翻译： 本发明的实施例提供一种高电压传输电路，包括高压传输电路的行解码器电路和包括高电压传输电路的非易失性半导体存储器件。 在一个实施例中，本发明提供了一种半导体存储器件的高电压传输电路，其包括高压开关，其包括高压晶体管，该高压晶体管包括经由第一耗尽型晶体管连接到升压电压的第一端子，并且包括连接到 经由第二耗尽型晶体管的输出节点。 高电压传输电路还包括适于响应于输入信号驱动第一和第二耗尽型晶体管和高压晶体管的驱动器电路。

公开(公告)号：US20060133144A1

公开(公告)日：2006-06-22

申请号：US11133214

申请日：2005-05-20

申请人： Jin-Yub Lee ,  Yong-Taek Jeong

发明人： Jin-Yub Lee ,  Yong-Taek Jeong

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C2216/14

摘要： Disclosed is a page buffer for a nonvolatile semiconductor memory device and a related method of operation. The page buffer includes a unidirectional driver between a loading latch unit used for storing a data bit in the page buffer and a bitline used to program a memory cell connected to the page buffer.

摘要翻译： 公开了一种用于非易失性半导体存储器件的页面缓冲器和相关的操作方法。 页缓冲器包括用于存储页缓冲器中的数据位的加载锁存单元与用于对连接到页缓冲器的存储单元进行编程的位线之间的单向驱动器。

公开(公告)号：US07515503B2

公开(公告)日：2009-04-07

申请号：US11634061

申请日：2006-12-06

申请人： Jong-Hoon Lee ,  Yong-Taek Jeong ,  Jin-Kook Kim

发明人： Jong-Hoon Lee ,  Yong-Taek Jeong ,  Jin-Kook Kim

IPC分类号： G11C8/00

CPC分类号： G11C8/08 ,  G11C11/419 ,  G11C16/08 ,  G11C16/12

摘要： Embodiments of the invention provide a high voltage transfer circuit, a row decoder circuit comprising the high voltage transfer circuit, and a non-volatile semiconductor memory device comprising the high voltage transfer circuit. In one embodiment, the invention provides a high voltage transfer circuit of a semiconductor memory device comprising a high voltage switch comprising a high voltage transistor comprising a first terminal connected to a boosted voltage via a first depletion-type transistor and comprising a second terminal connected to an output node via a second depletion-type transistor. The high voltage transfer circuit further comprises a driver circuit adapted to drive the first and second depletion-type transistors and the high voltage transistor in response to an input signal.

摘要翻译： 本发明的实施例提供一种高电压传输电路，包括高压传输电路的行解码器电路和包括高电压传输电路的非易失性半导体存储器件。 在一个实施例中，本发明提供了一种半导体存储器件的高电压传输电路，其包括高压开关，其包括高压晶体管，该高压晶体管包括经由第一耗尽型晶体管连接到升压电压的第一端子，并且包括连接到 经由第二耗尽型晶体管的输出节点。 高电压传输电路还包括适于响应于输入信号驱动第一和第二耗尽型晶体管和高压晶体管的驱动器电路。

公开(公告)号：US07684246B2

公开(公告)日：2010-03-23

申请号：US11465323

申请日：2006-08-17

申请人： Yong-Taek Jeong ,  Jin-Yub Lee

发明人： Yong-Taek Jeong ,  Jin-Yub Lee

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C5/145 ,  G11C16/30

摘要： A flash memory device may include a pump, a regulator to control the pump so that an output voltage of the pump is substantially maintained at a target voltage, and a control circuit to control the regulator so that the pump selectively generates a program voltage or an erase voltage. In some embodiments, the output voltage of the pump may be stepped in response to program loop iterations during a program operation, or set to a target voltage during an erase operation.

摘要翻译： 闪存器件可以包括泵，用于控制泵的调节器，使得泵的输出电压基本上保持在目标电压，以及控制电路以控制调节器，使得泵选择性地产生编程电压或 擦除电压。 在一些实施例中，泵的输出电压可以在编程操作期间响应于程序循环迭代而阶梯式，或者在擦除操作期间被设置为目标电压。

公开(公告)号：US07224624B2

公开(公告)日：2007-05-29

申请号：US11133214

申请日：2005-05-20

申请人： Jin-Yub Lee ,  Yong-Taek Jeong

发明人： Jin-Yub Lee ,  Yong-Taek Jeong

IPC分类号： G11C7/10 ,  G11C16/06

CPC分类号： G11C16/10 ,  G11C2216/14

摘要： Disclosed is a page buffer for a nonvolatile semiconductor memory device and a related method of operation. The page buffer includes a unidirectional driver between a loading latch unit used for storing a data bit in the page buffer and a bitline used to program a memory cell connected to the page buffer.

摘要翻译： 公开了一种用于非易失性半导体存储器件的页面缓冲器和相关的操作方法。 页缓冲器包括用于存储页缓冲器中的数据位的加载锁存单元与用于对连接到页缓冲器的存储单元进行编程的位线之间的单向驱动器。