公开(公告)号：US09136002B2

公开(公告)日：2015-09-15

申请号：US14242406

申请日：2014-04-01

Applicant: Yongkyu Lee ,  BoGeun Kim

Inventor： Yongkyu Lee ,  BoGeun Kim

IPC: G11C16/04 ,  G11C16/10 ,  G11C11/56 ,  G11C16/34 ,  G11C7/02 ,  G11C7/10

CPC classification number: G11C16/10 ,  G11C7/02 ,  G11C7/1006 ,  G11C11/5628 ,  G11C16/3418

Abstract: A data programming method of a semiconductor memory device is provided which includes randomizing write data using a randomization method selected from among a plurality of randomization methods according to whether the write data is programmed in one of a plurality of nonvolatile memories; and programming the randomized write data in at least one of the plurality of nonvolatile memories, wherein the plurality of nonvolatile memories has different types from one another.

Abstract translation: 提供一种半导体存储器件的数据编程方法，其包括使用根据所述写入数据是否被编程在多个非易失性存储器之一中的从多种随机化方法中选择的随机化方法来随机化写入数据; 以及将所述随机写入数据编程在所述多个非易失性存储器中的至少一个中，其中所述多个非易失性存储器具有彼此不同的类型。

公开(公告)号：US20110188310A1

公开(公告)日：2011-08-04

申请号：US13014237

申请日：2011-01-26

Applicant: BoGeun Kim

Inventor： BoGeun Kim

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C16/04 ,  G11C16/06

Abstract: A memory device includes a plurality of memory cells serially connected between a bit line and a common source line and a plurality of word lines, respective ones of which are connected to respective gates of the plurality of memory cells. The memory device further includes a common source line compensation circuit configured to generate a compensated bias voltage on the bit line or at least one of the plurality of word lines responsive to a common source line voltage on the common source line. Related methods of operating memory devices are also provided.

Abstract translation: 存储器件包括串联连接在位线和公共源极线和多个字线之间的多个存储器单元，其中各个字线连接到多个存储器单元的各个栅极。 存储器件还包括公共源极线补偿电路，该公共源极线补偿电路被配置为响应于公共源极线上的公共源极线电压而产生位线上的补偿偏置电压或多个字线中的至少一个字线。 还提供了操作存储器件的相关方法。

公开(公告)号：US08422292B2

公开(公告)日：2013-04-16

申请号：US13100134

申请日：2011-05-03

Applicant: Yoon-Hee Choi ,  BoGeun Kim

Inventor： Yoon-Hee Choi ,  BoGeun Kim

IPC: G11C11/34

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3454 ,  G11C2211/5621

Abstract: A nonvolatile memory device and a programming method thereof perform a programming verification step including a selective verification step and a sequential verification step. In the selective verification step, a data input/output (I/O) circuit selectively precharges a selected bit line according to a temporary programmed state of stored data. In the sequential verification step, the data I/O circuit selectively precharges each bit line according to the result of the previous selective verification step or a previous sequential verification step. According to the programming method, because a memory cell not requiring a programming verification step is not precharged in the programming verification step, an ON cell current does not flow therethrough. Accordingly, the current flowing through a common source line during verification can be reduced.

Abstract translation: 非易失性存储器件及其编程方法执行包括选择性验证步骤和顺序验证步骤的编程验证步骤。 在选择性验证步骤中，数据输入/输出（I / O）电路根据存储数据的临时编程状态选择性地对所选位线进行预充电。 在顺序验证步骤中，数据I / O电路根据先前的选择性验证步骤的结果或先前的顺序验证步骤选择性地预充电每一位线。 根据编程方法，由于在编程验证步骤中不需要编程验证步骤的存储单元未被预充电，所以ON单元电流不流过其中。 因此，可以减少在验证期间流过公共源极线的电流。

公开(公告)号：US08446769B2

公开(公告)日：2013-05-21

申请号：US13014237

申请日：2011-01-26

Applicant: BoGeun Kim

Inventor： BoGeun Kim

IPC: G11C11/34

CPC classification number: G11C16/04 ,  G11C16/06

Abstract: A memory device includes a plurality of memory cells serially connected between a bit line and a common source line and a plurality of word lines, respective ones of which are connected to respective gates of the plurality of memory cells. The memory device further includes a common source line compensation circuit configured to generate a compensated bias voltage on the bit line or at least one of the plurality of word lines responsive to a common source line voltage on the common source line. Related methods of operating memory devices are also provided.

Abstract translation: 存储器件包括串联连接在位线和公共源极线和多个字线之间的多个存储器单元，其中各个字线连接到多个存储器单元的各个栅极。 存储器件还包括公共源极线补偿电路，该公共源极线补偿电路被配置为响应于公共源极线上的公共源极线电压而产生位线上的补偿偏置电压或多个字线中的至少一个字线。 还提供了操作存储器件的相关方法。

公开(公告)号：US20110280083A1

公开(公告)日：2011-11-17

申请号：US13100134

申请日：2011-05-03

Applicant: Yoon-Hee Choi ,  BoGeun Kim

Inventor： Yoon-Hee Choi ,  BoGeun Kim

IPC: G11C16/10 ,  G11C16/06

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3454 ,  G11C2211/5621

Abstract: A nonvolatile memory device and a programming method thereof perform a programming verification step including a selective verification step and a sequential verification step. In the selective verification step, a data input/output (I/O) circuit selectively precharges a selected bit line according to a temporary programmed state of stored data. In the sequential verification step, the data I/O circuit selectively precharges each bit line according to the result of the previous selective verification step or a previous sequential verification step. According to the programming method, because a memory cell not requiring a programming verification step is not precharged in the programming verification step, an ON cell current does not flow therethrough. Accordingly, the current flowing through a common source line during verification can be reduced.

Abstract translation: 非易失性存储器件及其编程方法执行包括选择性验证步骤和顺序验证步骤的编程验证步骤。 在选择性验证步骤中，数据输入/输出（I / O）电路根据存储数据的临时编程状态选择性地对所选位线进行预充电。 在顺序验证步骤中，数据I / O电路根据先前的选择性验证步骤的结果或先前的顺序验证步骤选择性地预充电每一位线。 根据编程方法，由于在编程验证步骤中不需要编程验证步骤的存储单元未被预充电，所以ON单元电流不流过其中。 因此，可以减少在验证期间流过公共源极线的电流。

公开(公告)号：US09864682B2

公开(公告)日：2018-01-09

申请号：US14664125

申请日：2015-03-20

Applicant: Doohyun Kim ,  BoGeun Kim ,  Kitae Park ,  Jinman Han

Inventor： Doohyun Kim ,  BoGeun Kim ,  Kitae Park ,  Jinman Han

IPC: G06F12/02 ,  G11C11/56 ,  G11C16/04

CPC classification number: G06F12/0246 ,  G06F2212/7201 ,  G11C11/5621 ,  G11C16/0483

Abstract: According to example embodiments, a method of operating a storage device includes reading a process capability index using a memory controller, adjusting at least one operation condition based on the process capability index, and operating one of at least one nonvolatile memory device according to the at least one operation condition adjusted. The process capability index indicates how a structure associated with a memory cell to be operated deviates from a target shape.