公开(公告)号：US5693964A

公开(公告)日：1997-12-02

申请号：US670931

申请日：1996-06-26

申请人： Yorito Ohta ,  Kaoru Inoue ,  Mitsuru Tanabe

发明人： Yorito Ohta ,  Kaoru Inoue ,  Mitsuru Tanabe

IPC分类号： H01L21/285 ,  H01L21/335 ,  H01L21/338 ,  H01L29/778 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L29/66863 ,  H01L21/28587 ,  H01L29/66462 ,  H01L29/7783

摘要： A channel layer of n-type GaAs doped with Si as an impurity is formed on a GaAs semiinsulating substrate. A gate electrode of, for example, aluminum is formed on the channel layer. The gate electrode is in Schottky-contact with channel layer. Formed on opposite sides of the gate electrode on the channel layer are drain- and source side electric field relaxation layers of n-type In.sub.x G.sub.1-x As doped with impurities. Each electric field relaxation layer substantially produces a potential difference at its lateral edge portion by an electric current flowing across the lateral edge portion. A WSi drain electrode is formed on the drain-side electric field relaxation layer. A WSi source electrode is formed on the source-side electric field relaxation layer.

摘要翻译： 在GaAs半绝缘基板上形成掺杂有Si作为杂质的n型GaAs的沟道层。 在沟道层上形成例如铝的栅电极。 栅电极与沟道层肖特基接触。 在沟道层上的栅电极的相对侧上形成掺杂有杂质的n型In x Gd 1-x As的漏极和源极电场弛豫层。 每个电场弛豫层通过流过横向边缘部分的电流在其横向边缘部分基本上产生电位差。 在漏极侧电场弛豫层上形成WSi漏电极。 在源侧电场弛豫层上形成WSi源电极。

公开(公告)号：US6153499A

公开(公告)日：2000-11-28

申请号：US289946

申请日：1999-04-13

申请人： Yoshiharu Anda ,  Toshinobu Matsuno ,  Katsunori Nishii ,  Kaoru Inoue ,  Manabu Yanagihara ,  Mitsuru Tanabe

发明人： Yoshiharu Anda ,  Toshinobu Matsuno ,  Katsunori Nishii ,  Kaoru Inoue ,  Manabu Yanagihara ,  Mitsuru Tanabe

IPC分类号： H01L21/28 ,  H01L21/027 ,  H01L21/285 ,  H01L21/338 ,  H01L21/768 ,  H01L29/812 ,  H01L21/44

CPC分类号： H01L21/28581 ,  H01L21/0271 ,  H01L21/0277 ,  H01L21/76816 ,  Y10S438/949

摘要： A first resist film for EB exposure, a buffer film, and a second resist film for i-line exposure are applied sequentially onto a substrate. Thereafter, the second resist film and the buffer film are subjected to patterning for forming a first opening. Then, dry etching is performed with respect to the first resist film masked with the second resist film to transfer the pattern of the second resist film to the first resist film and thereby form a second opening in the first resist film. Subsequently, a third resist film of chemically amplified type is applied to the entire surface of the first resist film to form a mixing layer in conjunction with the first resist film. As a result, the wall faces of the second opening are covered with the mixing layer and the width of the second opening is thereby reduced.

摘要翻译： 用于EB曝光的第一抗蚀剂膜，缓冲膜和用于i线曝光的第二抗蚀剂膜顺序地施加到基板上。 此后，对第二抗蚀剂膜和缓冲膜进行用于形成第一开口的图案化。 然后，相对于用第二抗蚀剂膜掩蔽的第一抗蚀剂膜进行干蚀刻，将第二抗蚀剂膜的图案转印到第一抗蚀剂膜上，从而在第一抗蚀剂膜中形成第二开口。 随后，将化学放大型的第三抗蚀剂膜施加到第一抗蚀剂膜的整个表面上以与第一抗蚀剂膜结合形成混合层。 结果，第二开口的壁面被混合层覆盖，从而减小了第二开口的宽度。

公开(公告)号：US20120036350A1

公开(公告)日：2012-02-09

申请号：US13189673

申请日：2011-07-25

申请人： Hiroshi Kuno ,  Mitsuru Tanabe ,  Kenjiro Ueda ,  Koji Yoshimura

发明人： Hiroshi Kuno ,  Mitsuru Tanabe ,  Kenjiro Ueda ,  Koji Yoshimura

IPC分类号： H04L9/00

CPC分类号： H04N21/8358 ,  H04N21/8456

摘要： An information processing apparatus includes a data processing unit which generates content to be distributed to a client; and a communication unit which sends the content generated by the data processing unit, wherein the data processing unit combines a plurality of watermarking record blocks, each of which is obtained by embedding watermarking data into a block as section data of the content, generates content in which different watermarking data sequences are set in units of distribution processing with respect to the clients, and sends the generated content to the clients through the communication unit.

摘要翻译： 信息处理设备包括：数据处理单元，生成要分发给客户端的内容; 以及通信单元，其发送由数据处理单元生成的内容，其中数据处理单元组合多个水印记录块，每个水印记录块通过将水印数据嵌入到作为内容的区段数据的块中而获得，生成内容 以相对于客户机的分发处理为单位设置不同的水印数据序列，并且通过通信单元将生成的内容发送给客户端。

公开(公告)号：US07437768B2

公开(公告)日：2008-10-14

申请号：US11252750

申请日：2005-10-19

申请人： Itaru Kawakami ,  Ryuji Ishiguro ,  Mitsuru Tanabe ,  Yuichi Ezura

发明人： Itaru Kawakami ,  Ryuji Ishiguro ,  Mitsuru Tanabe ,  Yuichi Ezura

IPC分类号： H04L9/00

CPC分类号： G06F21/10 ,  G06F17/30044 ,  G06F17/30949 ,  G06F21/121 ,  G06F2221/0797 ,  G11B20/00086 ,  G11B20/00181 ,  G11B20/0021 ,  G11B20/00753 ,  G11B20/00789 ,  G11B20/00797 ,  G11B20/0084 ,  G11B20/00855 ,  G11B20/10 ,  G11B2020/00043 ,  G11B2020/00057

摘要： The CPU 11 of the personal computer 1 controls the CPU 32 of the adaptor 26 made of a semiconductor ID to compute a hash value of a content-managing music data base recorded in the HDD 21 and store it into the nonvolatile memory 34. When playing back a content recorded in the HDD 21, the CPU 11 computes the hash value of the music data base recorded in the HDD 21, compares it with hash values stored cumulatively in the nonvolatile memory 34, and controls the playback of the content from the HDD 21 based on the result of the comparison.

摘要翻译： 个人计算机1的CPU 11控制由半导体ID构成的适配器26的CPU32，以计算记录在HDD 21中的内容管理音乐数据库的哈希值并将其存储到非易失性存储器34中。 当重放记录在HDD 21中的内容时，CPU 11计算记录在HDD 21中的音乐数据库的哈希值，并将其与累积地存储在非易失性存储器34中的哈希值进行比较，并且控制内容的回放 HDD 21基于比较结果。

公开(公告)号：US07162316B2

公开(公告)日：2007-01-09

申请号：US11081632

申请日：2005-03-17

申请人： Mitsuyuki Hatanaka ,  Mitsuru Tanabe

发明人： Mitsuyuki Hatanaka ,  Mitsuru Tanabe

IPC分类号： G06F17/00

CPC分类号： G10L19/0212 ,  G10L19/00 ,  G10L19/0019 ,  G11B20/10527 ,  G11B2020/00043 ,  G11B2020/10546 ,  H03M7/30

摘要： In order to obtain coded data which does not strike viewers and listeners as being incongruous, when plural audio data are to be coded, a coding program groups the respective audio data into one audio data, codes the grouped audio data in sequence with a predetermined number of samples being treated as units, and sets delimitations corresponding to the delimitations of the plural audio data in the coded data at coding units of the coded data.

摘要翻译： 为了获得不使观众和听众不合理的编码数据，当要对多个音频数据进行编码时，编码程序将各个音频数据分组成一个音频数据，按照预定的数量对分组的音频数据进行编码 被处理为单位，并且以编码数据的编码单位设置与编码数据中的多个音频数据的分界对应的定界。

公开(公告)号：US20060047978A1

公开(公告)日：2006-03-02

申请号：US11252750

申请日：2005-10-19

申请人： Itaru Kawakami ,  Ryuji Ishiguro ,  Mitsuru Tanabe ,  Yuichi Ezura

发明人： Itaru Kawakami ,  Ryuji Ishiguro ,  Mitsuru Tanabe ,  Yuichi Ezura

IPC分类号： G06F12/14

CPC分类号： G06F21/10 ,  G06F17/30044 ,  G06F17/30949 ,  G06F21/121 ,  G06F2221/0797 ,  G11B20/00086 ,  G11B20/00181 ,  G11B20/0021 ,  G11B20/00753 ,  G11B20/00789 ,  G11B20/00797 ,  G11B20/0084 ,  G11B20/00855 ,  G11B20/10 ,  G11B2020/00043 ,  G11B2020/00057

摘要： The CPU 11 of the personal computer 1 controls the CPU 32 of the adaptor 26 made of a semiconductor ID to compute a hash value of a content-managing music data base recorded in the HDD 21 and store it into the nonvolatile memory 34. When playing back a content recorded in the HDD 21, the CPU 11 computes the hash value of the music data base recorded in the HDD 21, compares it with hash values stored cumulatively in the nonvolatile memory 34, and controls the playback of the content from the HDD 21 based on the result of the comparison.

摘要翻译： 个人计算机1的CPU 11控制由半导体ID构成的适配器26的CPU32，以计算记录在HDD 21中的内容管理音乐数据库的哈希值，并将其存储到非易失性存储器34中。当播放时 返回记录在HDD 21中的内容，CPU 11计算记录在HDD 21中的音乐数据库的散列值，将其与累积地存储在非易失性存储器34中的散列值进行比较，并控制来自HDD的内容的回放 21基于比较的结果。

公开(公告)号：US06747297B2

公开(公告)日：2004-06-08

申请号：US10219298

申请日：2002-08-16

申请人： Mitsuru Tanabe

发明人： Mitsuru Tanabe

IPC分类号： H01L2348

CPC分类号： H01L29/7784

摘要： An undoped In0.52Al0.48As buffer layer (thickness: 500 nm), an undoped In0.53Ga0.47As channel layer (thickness: 30 nm), an n-type delta doped layer for shortening the distance between the channel layer and a gate electrode and attaining a desired carrier density, an undoped In0.52Al0.48As Schottky layer, and an n-type In0.53Ga0.47As cap layer doped with Si (thickness: 50 nm) are formed in this order on the principal surface of an Fe-doped InP semi-insulating substrate. An n-type GaAs protective layer doped with Si (thickness: 7.5 nm) is formed between the cap layer and source/drain electrodes for protecting the cap layer.

摘要翻译： 未掺杂的In0.52Al0.48As缓冲层（厚度：500nm），未掺杂的In0.53Ga0.47As沟道层（厚度：30nm），n型δ掺杂层，用于缩短沟道层和栅极之间的距离 电极并获得所需的载流子密度，掺杂有Si（厚度：50nm）的未掺杂的In0.52Al0.48As肖特基层和n型In 0.53 Ga 0.47 As覆盖层依次形成在 Fe掺杂InP半绝缘基板。 在盖层和源极/漏极之间形成掺杂有Si（厚度：7.5nm）的n型GaAs保护层，用于保护盖层。

公开(公告)号：US09100105B2

公开(公告)日：2015-08-04

申请号：US14237591

申请日：2012-08-10

申请人： Yasuko Yamamoto ,  Mitsuru Tanabe ,  Mitsuru Maeda ,  Kenji Kuniyoshi

发明人： Yasuko Yamamoto ,  Mitsuru Tanabe ,  Mitsuru Maeda ,  Kenji Kuniyoshi

IPC分类号： H04B3/00 ,  H04L25/00 ,  H04B3/56 ,  H04B3/54

CPC分类号： H04B3/56 ,  H04B3/54 ,  H04B2203/5425 ,  H04B2203/5483 ,  H04B2203/5491

摘要： A splitter includes, in parallel between trunk terminals and branch terminals, a signal branching circuit that blocks distributed power and passes a PLC communication signal and a power branching circuit that blocks the communication signal and passes the distributed power. In the signal branching circuit, impedance viewed from the branch terminal side is matched with characteristic impedance of a power line and impedance viewed from the trunk terminal side is higher than impedance viewed from the branch terminal side, in the frequency band of the communication signal. In the power branching circuit, input/output impedance is set to be sufficiently higher than the impedance of the signal branching circuit viewed from the trunk terminal side, in the frequency band of the communication signal.

摘要翻译： 分路器在中继线端子和分支端子之间并联包括阻塞分布式电力并通过PLC通信信号的信号分支电路和阻塞通信信号并通过分布式电力的功率分支电路。 在信号分支电路中，在通信信号的频带中，从分支端子侧观察的阻抗与电力线的特性阻抗匹配，并且从主体侧端子侧观察的阻抗高于从分支端子侧观察到的阻抗。 在功率分支电路中，在通信信号的频带中，输入/输出阻抗被设定为足够高于从主体端子侧观察的信号分支电路的阻抗。

公开(公告)号：US20100318790A1

公开(公告)日：2010-12-16

申请号：US12793733

申请日：2010-06-04

申请人： Hiroshi Kuno ,  Mitsuru Tanabe ,  Koji Yoshimura ,  Daisaku Hayashi

发明人： Hiroshi Kuno ,  Mitsuru Tanabe ,  Koji Yoshimura ,  Daisaku Hayashi

IPC分类号： H04L9/32 ,  G06F12/02

CPC分类号： H04L9/0844 ,  G06F2221/2135 ,  H04L9/3273 ,  H04L2209/605

摘要： A card management device includes: a card device configured to include a controller on which a cryptographic IP is mounted in advance; and an individual information writing device configured to allow the card device to be connected to the individual information writing device in such a way that the card device is capable of data transfer to the individual information writing device, individual information assigned to the card device in advance being set in the individual information writing device, the individual information writing device being capable of writing the individual information to the card device connected to the individual information writing device.

摘要翻译： 卡管理装置包括：卡装置，被配置为包括预先安装有加密IP的控制器; 以及个人信息写入装置，被配置为允许卡装置以与卡装置能够数据传送到个人信息写入装置的方式连接到个人信息写入装置，预先分配给卡装置的个人信息 设置在个人信息写入装置中，个人信息写入装置能够将个人信息写入连接到个人信息写入装置的卡装置。

公开(公告)号：US07282979B2

公开(公告)日：2007-10-16

申请号：US11226295

申请日：2005-09-15

申请人： Takatoshi Tanaka ,  Mitsuru Tanabe ,  Shigeru Kataoka

发明人： Takatoshi Tanaka ,  Mitsuru Tanabe ,  Shigeru Kataoka

IPC分类号： H03H11/16

CPC分类号： H03L7/0812 ,  H03H7/20 ,  H03H11/20 ,  H03K2005/00286

摘要： A phase shifting device includes a signal source; a variable phase shifter; first and second doubling circuits; and a 90-degree phase comparator. An output from the signal source is connected to an input of the variable phase shifter and to an input of the second doubling circuit, an output from the variable phase shifter is connected to an input of the first doubling circuit, an output from the first doubling circuit serves as a first output signal, and an output from the second doubling circuit serves as a second output signal. The first output signal and the second output signal are inputted to the 90-degree phase comparator. The amount of phase shift rotation of the variable phase shifter is changed by a phase shift control signal outputted from the 90-degree phase comparator. By this, an exact 90-degree phase shift is obtained.

摘要翻译： 相移装置包括信号源; 可变移相器 第一和第二加倍电路; 和90度相位比较器。 来自信号源的输出连接到可变移相器的输入端和第二倍频电路的输入端，可变移相器的输出端连接到第一倍频电路的输入端，第一倍频输出端 电路用作第一输出信号，并且来自第二倍频电路的输出用作第二输出信号。 第一输出信号和第二输出信号被输入到90度相位比较器。 可变移相器的相移旋转量由从90度相位比较器输出的相移控制信号改变。 由此可以得到精确的90度相移。