公开(公告)号：US6153499A

公开(公告)日：2000-11-28

申请号：US289946

申请日：1999-04-13

申请人： Yoshiharu Anda ,  Toshinobu Matsuno ,  Katsunori Nishii ,  Kaoru Inoue ,  Manabu Yanagihara ,  Mitsuru Tanabe

发明人： Yoshiharu Anda ,  Toshinobu Matsuno ,  Katsunori Nishii ,  Kaoru Inoue ,  Manabu Yanagihara ,  Mitsuru Tanabe

IPC分类号： H01L21/28 ,  H01L21/027 ,  H01L21/285 ,  H01L21/338 ,  H01L21/768 ,  H01L29/812 ,  H01L21/44

CPC分类号： H01L21/28581 ,  H01L21/0271 ,  H01L21/0277 ,  H01L21/76816 ,  Y10S438/949

摘要： A first resist film for EB exposure, a buffer film, and a second resist film for i-line exposure are applied sequentially onto a substrate. Thereafter, the second resist film and the buffer film are subjected to patterning for forming a first opening. Then, dry etching is performed with respect to the first resist film masked with the second resist film to transfer the pattern of the second resist film to the first resist film and thereby form a second opening in the first resist film. Subsequently, a third resist film of chemically amplified type is applied to the entire surface of the first resist film to form a mixing layer in conjunction with the first resist film. As a result, the wall faces of the second opening are covered with the mixing layer and the width of the second opening is thereby reduced.

摘要翻译： 用于EB曝光的第一抗蚀剂膜，缓冲膜和用于i线曝光的第二抗蚀剂膜顺序地施加到基板上。 此后，对第二抗蚀剂膜和缓冲膜进行用于形成第一开口的图案化。 然后，相对于用第二抗蚀剂膜掩蔽的第一抗蚀剂膜进行干蚀刻，将第二抗蚀剂膜的图案转印到第一抗蚀剂膜上，从而在第一抗蚀剂膜中形成第二开口。 随后，将化学放大型的第三抗蚀剂膜施加到第一抗蚀剂膜的整个表面上以与第一抗蚀剂膜结合形成混合层。 结果，第二开口的壁面被混合层覆盖，从而减小了第二开口的宽度。

公开(公告)号：US06051454A

公开(公告)日：2000-04-18

申请号：US151357

申请日：1998-09-10

申请人： Yoshiharu Anda ,  Toshinobu Matsuno ,  Manabu Yanagihara ,  Mitsuru Tanabe ,  Toshiaki Matsui ,  Nobumitsu Hirose

发明人： Yoshiharu Anda ,  Toshinobu Matsuno ,  Manabu Yanagihara ,  Mitsuru Tanabe ,  Toshiaki Matsui ,  Nobumitsu Hirose

IPC分类号： H01L21/285 ,  H01L21/335 ,  H01L21/338

CPC分类号： H01L29/66462 ,  H01L21/28587 ,  Y10S438/95

摘要： A lower resist film, which is made of PMMA for EB exposure and has a thickness of about 200 nm, is applied onto a substrate, and then an upper resist film to be exposed to i-rays is applied on the lower resist film. Thereafter, a mixed layer, in which the upper and lower resist films are mixed, is formed in the interface between the upper and lower resist films. Next, the upper resist film, except for the head-forming region thereof, is exposed to i-rays and developed, thereby forming an upper-layer opening. And then the mixed layer and a leg-forming region of the lower resist film are exposed to EB and developed, thereby forming a lower-layer opening having an upper part like a taper progressively expanding upward.

摘要翻译： 将用于EB曝光的PMMA制成并具有约200nm厚度的较低抗蚀剂膜施加到基板上，然后在下抗蚀剂膜上施加暴露于i射线的上抗蚀剂膜。 此后，在上下抗蚀剂膜之间的界面中形成混合有上下抗蚀剂膜的混合层。 接下来，将除了其头部形成区域之外的上抗蚀剂膜暴露于i射线并显影，从而形成上层开口。 然后将下层抗蚀剂膜的混合层和腿部形成区域暴露于EB并显影，从而形成具有逐渐向上扩展的锥形的上部的下层开口。

公开(公告)号：US06570464B1

公开(公告)日：2003-05-27

申请号：US09648498

申请日：2000-08-25

申请人： Mitsuru Tanabe ,  Mitsuru Nishitsuji ,  Yoshiharu Anda

发明人： Mitsuru Tanabe ,  Mitsuru Nishitsuji ,  Yoshiharu Anda

IPC分类号： H01P500

CPC分类号： H01P3/003 ,  H01P11/003

摘要： A high frequency apparatus includes a dielectric substrate having a surface including a first area and at least one second area; a first dielectric thin layer provided on a portion of a first area; and a uniplanar transmission line provided on the first dielectric thin layer and on a portion of the second area, the uniplanar transmission line extending, continuously on the second area and the first dielectric thin layer.

摘要翻译： 高频装置包括具有包括第一区域和至少一个第二区域的表面的电介质基板; 设置在第一区域的一部分上的第一电介质薄层; 以及设置在所述第一电介质薄层上和所述第二区域的一部分上的所述单面传输线，所述单面传输线在所述第二区域和所述第一电介质薄层上连续地延伸。

公开(公告)号：US20120153355A1

公开(公告)日：2012-06-21

申请号：US13402631

申请日：2012-02-22

申请人： Hidekazu UMEDA ,  Yoshiharu Anda ,  Tetsuzo Ueda ,  Tsuyoshi Tanaka ,  Daisuke Ueda

发明人： Hidekazu UMEDA ,  Yoshiharu Anda ,  Tetsuzo Ueda ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC分类号： H01L29/78

CPC分类号： H01L29/2003 ,  H01L29/1066 ,  H01L29/4175 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/861

摘要： A nitride semiconductor device includes a semiconductor substrate, and a nitride semiconductor layer formed on the semiconductor substrate. The semiconductor substrate includes a normal region and an interface current block region surrounding the normal region. The nitride semiconductor layer includes an element region and an isolation region surrounding the element region. The element region is formed over the normal region. The interface current block region contains impurities, and forms a potential barrier against carriers generated at an interface between the nitride semiconductor layer and the semiconductor substrate.

摘要翻译： 氮化物半导体器件包括半导体衬底和形成在半导体衬底上的氮化物半导体层。 半导体衬底包括正常区域和围绕法线区域的界面电流阻挡区域。 氮化物半导体层包括元件区域和围绕元件区域的隔离区域。 元件区域形成在正常区域上。 界面电流阻挡区域含有杂质，并且在氮化物半导体层和半导体衬底之间的界面处产生的载流子形成势垒。

公开(公告)号：US20090309134A1

公开(公告)日：2009-12-17

申请号：US12423347

申请日：2009-04-14

申请人： Akihiko Nishio ,  Yoshiaki Shimada ,  Yoshiaki Kato ,  Yoshiharu Anda

发明人： Akihiko Nishio ,  Yoshiaki Shimada ,  Yoshiaki Kato ,  Yoshiharu Anda

IPC分类号： H01L29/812 ,  H01L21/335

CPC分类号： H01L29/66462 ,  H01L29/7787

摘要： A multilayer structure including a first electron supply layer and a second electron supply layer is used for an electron supply layer. A multilayer structure including an SiN film and an SiO2 film is used for an insulating film to be formed on the surface of a semiconductor. In forming an opening for exposing the electron supply layer in the insulating film, the SiN film that is in contact with the semiconductor is side-etched. Accordingly, it is possible to avoid a contact between a gate electrode and a portion, which is located on the side of the electron supply layer, of the inner peripheral surface of the opening, and further to expose only the second electron supply layer in the vicinity of the gate electrode.

摘要翻译： 包括第一电子供应层和第二电子供应层的多层结构被用于电子供应层。 使用包括SiN膜和SiO 2膜的多层结构来形成在半导体的表面上的绝缘膜。 在形成用于暴露绝缘膜中的电子供给层的开口时，与半导体接触的SiN膜被侧蚀刻。 因此，可以避免栅电极与位于电子供给层一侧的部分之间的开口的内周面的接触，并且还可以仅暴露于第二电子供给层 栅电极附近。

公开(公告)号：US07199014B2

公开(公告)日：2007-04-03

申请号：US11000239

申请日：2004-12-01

申请人： Yoshiharu Anda

发明人： Yoshiharu Anda

IPC分类号： H01L21/336

CPC分类号： H01L29/66462 ,  H01L29/7784

摘要： There is provided a field effect transistor which is suitable for a power amplifier application or the like, and have a double recess structure with superior repeatability. A film thickness of an AlGaAs layer can determine a depth of a second step of a recess uniquely by using the AlGaAs layer and an InGaP layer with a higher etching selection ratio, a double recess structure can be formed with desirable repeatability, and a high withstand voltage device suitable for a power amplifier application or the like is achieved by making both side surfaces of a gate electrode into the AlGaAs layer.

摘要翻译： 提供了适用于功率放大器应用等的场效应晶体管，并且具有优异的重复性的双凹槽结构。 AlGaAs层的膜厚度可以通过使用AlGaAs层和具有较高蚀刻选择比的InGaP层来唯一地确定凹部的第二阶梯深度，可以形成具有所需重复性的双凹槽结构，并且具有高耐受性 通过使栅电极的两个侧表面成为AlGaAs层来实现适用于功率放大器应用等的电压装置。

公开(公告)号：US06967360B2

公开(公告)日：2005-11-22

申请号：US10617793

申请日：2003-07-14

申请人： Yoshiharu Anda ,  Akiyoshi Tamura

发明人： Yoshiharu Anda ,  Akiyoshi Tamura

IPC分类号： H01L21/28 ,  H01L21/335 ,  H01L21/338 ,  H01L29/423 ,  H01L29/47 ,  H01L29/778 ,  H01L29/812 ,  H01L29/872 ,  H01L31/0328

CPC分类号： H01L29/66462 ,  H01L29/475 ,  H01L29/7784

摘要： A semiconductor device and its manufacturing method. The semiconductor device has a semi-insulating GaAs substrate 310, a GaAs buffer layer 321 that is formed on the semi-insulating GaAs substrate 310, AlGaAs buffer layer 322, a channel layer 323, a spacer layer 324, a carrier supply layer 325, a spacer layer 326, a Schottky layer 327 composed of an undoped In0.48Ga0.52P material, and an n+-type GaAs cap layer 328. A gate electrode 330 is formed on the Schottky layer 327, and is composed of LaB6 and has a Schottky contact with the Schottky layer 327, and ohmic electrodes 340 are formed on the n+-type GaAs cap layer 328.

摘要翻译： 一种半导体器件及其制造方法。 半导体器件具有半绝缘GaAs衬底310，形成在半绝缘GaAs衬底310上的GaAs缓冲层321，AlGaAs缓冲层322，沟道层323，间隔层324，载流子供应层325， 间隔层326，由未掺杂的In 0.48 Ga 0.52 P材料构成的肖特基层327和n + 栅电极330形成在肖特基层327上，由LaB 6构成，与肖特基层327具有肖特基接触，并且欧姆电极340形成在第n + +型GaAs覆盖层328。

公开(公告)号：US08872227B2

公开(公告)日：2014-10-28

申请号：US13402631

申请日：2012-02-22

申请人： Hidekazu Umeda ,  Yoshiharu Anda ,  Tetsuzo Ueda ,  Tsuyoshi Tanaka ,  Daisuke Ueda

发明人： Hidekazu Umeda ,  Yoshiharu Anda ,  Tetsuzo Ueda ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC分类号： H01L29/66 ,  H01L29/778 ,  H01L29/417 ,  H01L29/20

CPC分类号： H01L29/2003 ,  H01L29/1066 ,  H01L29/4175 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/861

摘要： A nitride semiconductor device includes a semiconductor substrate, and a nitride semiconductor layer formed on the semiconductor substrate. The semiconductor substrate includes a normal region and an interface current block region surrounding the normal region. The nitride semiconductor layer includes an element region and an isolation region surrounding the element region. The element region is formed over the normal region. The interface current block region contains impurities, and forms a potential barrier against carriers generated at an interface between the nitride semiconductor layer and the semiconductor substrate.

摘要翻译： 氮化物半导体器件包括半导体衬底和形成在半导体衬底上的氮化物半导体层。 半导体衬底包括正常区域和围绕法线区域的界面电流阻挡区域。 氮化物半导体层包括元件区域和围绕元件区域的隔离区域。 元件区域形成在正常区域上。 界面电流阻挡区域含有杂质，并且在氮化物半导体层和半导体衬底之间的界面处产生的载流子形成势垒。

公开(公告)号：US20060237753A1

公开(公告)日：2006-10-26

申请号：US11388545

申请日：2006-03-24

申请人： Yoshiharu Anda ,  Akiyoshi Tamura ,  Mitsuru Nishitsuji

发明人： Yoshiharu Anda ,  Akiyoshi Tamura ,  Mitsuru Nishitsuji

IPC分类号： H01L31/112

CPC分类号： H01L29/7784 ,  H01L21/28575 ,  H01L21/28587 ,  H01L29/66462

摘要： A field effect transistor according to the present invention includes a channel layer formed above a semi-insulating substrate, a Schottky layer formed above the channel layer, a gate electrode formed on the Schottky layer, Ohmic contact layers that are located above the Schottky layer with the gate electrode interposed therebetween and formed of InGaAs, and a source electrode and a drain electrode that are formed on the Ohmic contact layers. The source electrode, the drain electrode and the gate electrode have a layered structure in which their corresponding layers are formed of the same material, a lowermost layer is a WSi layer and a layer containing Al is provided above the lowermost layer. A field effect transistor that has an electrode resistance equivalent to a conventional level and can reduce a cost of manufacturing a field effect transistor and a method for manufacturing the same are provided.

摘要翻译： 根据本发明的场效应晶体管包括形成在半绝缘衬底上的沟道层，形成在沟道层上方的肖特基层，形成在肖特基层上的栅电极，位于肖特基层上方的欧姆接触层， 介于其间并由InGaAs形成的栅电极以及形成在欧姆接触层上的源电极和漏电极。 源电极，漏电极和栅电极具有层叠结构，其相应的层由相同的材料形成，最下层是WSi层，并且在最下层上设置含有Al的层。 提供具有等同于常规水平的电极电阻并且可以降低制造场效应晶体管的成本的场效应晶体管及其制造方法。

公开(公告)号：US20050139868A1

公开(公告)日：2005-06-30

申请号：US11000239

申请日：2004-12-01

申请人： Yoshiharu Anda

发明人： Yoshiharu Anda

IPC分类号： H01L29/417 ,  H01L21/335 ,  H01L21/338 ,  H01L29/47 ,  H01L29/778 ,  H01L29/812 ,  H01L29/872 ,  H01S5/00 ,  H01L29/745 ,  H01L29/76

CPC分类号： H01L29/66462 ,  H01L29/7784

摘要： There is provided a field effect transistor which is suitable for a power amplifier application or the like, and have a double recess structure with superior repeatability. A film thickness of an AlGaAs layer can determine a depth of a second step of a recess uniquely by using the AlGaAs layer and an InGaP layer with a higher etching selection ratio, a double recess structure can be formed with desirable repeatability, and a high withstand voltage device suitable for a power amplifier application or the like is achieved by making both side surfaces of a gate electrode into the AlGaAs layer.

摘要翻译： 提供了适用于功率放大器应用等的场效应晶体管，并且具有优异的重复性的双凹槽结构。 AlGaAs层的膜厚度可以通过使用AlGaAs层和具有较高蚀刻选择比的InGaP层来唯一地确定凹部的第二阶梯深度，可以形成具有所需重复性的双凹槽结构，并且具有高耐受性 通过使栅电极的两个侧表面成为AlGaAs层来实现适用于功率放大器应用等的电压装置。