公开(公告)号：US20120168838A1

公开(公告)日：2012-07-05

申请号：US13419947

申请日：2012-03-14

申请人： Takao MARUKAME ,  Mizue Ishikawa ,  Tomoaki Inokuchi ,  Hideyuki Sugiyama ,  Yoshiaki Saito

发明人： Takao MARUKAME ,  Mizue Ishikawa ,  Tomoaki Inokuchi ,  Hideyuki Sugiyama ,  Yoshiaki Saito

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/66984 ,  H01L21/823814 ,  H01L21/84 ,  H01L21/845 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/49 ,  H01L29/66075

摘要： A semiconductor device according to an embodiment includes: a semiconductor layer; source and drain regions in the semiconductor layer; a magnetic metal semiconductor compound film on each of the source and drain regions, the magnetic metal semiconductor compound film including the same semiconductor as a semiconductor of the semiconductor layer and a magnetic metal; a gate insulating film on the semiconductor layer between the source region and the drain region; a gate electrode on the gate insulating film; a gate sidewall formed at a side portion of the gate electrode, the gate sidewall being made of an insulating material; a film stack formed on the magnetic metal semiconductor compound film on each of the source and drain regions, the film stack including a magnetic layer; and an oxide layer formed on the gate sidewall, the oxide layer containing the same element as an element in the film stack.

摘要翻译： 根据实施例的半导体器件包括：半导体层; 半导体层中的源极和漏极区域; 在源极和漏极区域中的每一个上的磁性金属半导体化合物膜，包括与半导体层的半导体相同的半导体的磁性金属半导体化合物膜和磁性金属; 源极区域和漏极区域之间的半导体层上的栅极绝缘膜; 栅极绝缘膜上的栅电极; 栅极侧壁，其形成在所述栅电极的侧部，所述栅极侧壁由绝缘材料制成; 在所述源极和漏极区域中的每一个上形成在所述磁性金属半导体化合物膜上的膜堆叠，所述膜堆叠包括磁性层; 以及形成在栅极侧壁上的氧化物层，所述氧化物层包含与膜堆叠中的元件相同的元件。

公开(公告)号：US08026561B2

公开(公告)日：2011-09-27

申请号：US12725561

申请日：2010-03-17

申请人： Yoshiaki Saito ,  Hideyuki Sugiyama ,  Tomoaki Inokuchi ,  Takao Marukame ,  Mizue Ishikawa

发明人： Yoshiaki Saito ,  Hideyuki Sugiyama ,  Tomoaki Inokuchi ,  Takao Marukame ,  Mizue Ishikawa

IPC分类号： H01L21/02

CPC分类号： H01L43/02 ,  B01D53/1493 ,  B01D53/62 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1695 ,  H01L28/00 ,  H01L29/0843 ,  H01L29/0895 ,  H01L29/66984 ,  H01L43/10

摘要： A spin MOSFET includes: a first ferromagnetic layer provided on an upper face of a semiconductor substrate, and having a fixed magnetization direction perpendicular to a film plane; a semiconductor layer provided on an upper face of the first ferromagnetic layer, including a lower face opposed to the upper face of the first ferromagnetic layer, an upper face opposed to the lower face, and side faces different from the lower face and the upper face; a second ferromagnetic layer provided on the upper face of the semiconductor layer, and having a variable magnetization direction perpendicular to a film plane; a first tunnel barrier provided on an upper face of the second ferromagnetic layer; a third ferromagnetic layer provided on an upper face of the first tunnel barrier; a gate insulating film provided on the side faces of the semiconductor layer; and a gate electrode provided on the side faces of the semiconductor layer with the gate insulating film being interposed therebetween.

摘要翻译： 自旋MOSFET包括：设置在半导体衬底的上表面上并且具有与膜平面垂直的固定磁化方向的第一铁磁层; 设置在所述第一铁磁层的上表面上的半导体层，包括与所述第一铁磁层的上表面相对的下表面，与所述下表面相对的上表面，以及与所述下表面和所述上表面不同的侧面 ; 第二铁磁层，设置在所述半导体层的上表面上，并且具有与膜平面垂直的可变磁化方向; 设置在所述第二铁磁层的上表面上的第一隧道势垒; 设置在所述第一隧道屏障的上表面上的第三铁磁层; 设置在所述半导体层的侧面上的栅极绝缘膜; 以及设置在半导体层的侧面上的栅电极，其间插入有栅极绝缘膜。

公开(公告)号：US08405443B2

公开(公告)日：2013-03-26

申请号：US13419555

申请日：2012-03-14

申请人： Hideyuki Sugiyama ,  Tetsufumi Tanamoto ,  Takao Marukame ,  Mizue Ishikawa ,  Tomoaki Inokuchi ,  Yoshiaki Saito

发明人： Hideyuki Sugiyama ,  Tetsufumi Tanamoto ,  Takao Marukame ,  Mizue Ishikawa ,  Tomoaki Inokuchi ,  Yoshiaki Saito

IPC分类号： H03K17/687

CPC分类号： H01L27/112 ,  H03K19/17736

摘要： A pass transistor circuit according to an embodiment includes: a first input/output terminal connected to a first signal line; a second input/output terminal connected to a second signal line; a first device having a first terminal connected to a first power supply and a second terminal; a second device having a third terminal connected to the second terminal and a fourth terminal connected to a second power supply; a first transistor having one of source/drain connected to the second terminal, a gate receiving a first control signal; and a second transistor having a gate connected to the other one of source/drain of the first transistor, one of source/drain connected to the first input/output terminal, and the other one of source/drain connected to the second input/output terminal. One of the first and second devices is a nonvolatile memory device, the other one of the first and second devices is a MOSFET.

摘要翻译： 根据实施例的传输晶体管电路包括：连接到第一信号线的第一输入/输出端子; 连接到第二信号线的第二输入/输出端子; 第一装置，具有连接到第一电源和第二端子的第一端子; 第二装置，具有连接到第二端子的第三端子和连接到第二电源的第四端子; 第一晶体管，其源极/漏极中的一个连接到第二端子，栅极接收第一控制信号; 以及第二晶体管，其栅极连接到第一晶体管的源极/漏极中的另一个，栅极/漏极中的一个连接到第一输入/输出端子，另一个源极/漏极连接到第二输入/输出端 终奌站。 第一和第二器件中的一个是非易失性存储器件，第一和第二器件中的另一个是MOSFET。

公开(公告)号：US20120223762A1

公开(公告)日：2012-09-06

申请号：US13419555

申请日：2012-03-14

申请人： Hideyuki Sugiyama ,  Tetsufumi Tanamoto ,  Takao Marukame ,  Mizue Ishikawa ,  Tomoaki Inokuchi ,  Yoshiaki Saito

发明人： Hideyuki Sugiyama ,  Tetsufumi Tanamoto ,  Takao Marukame ,  Mizue Ishikawa ,  Tomoaki Inokuchi ,  Yoshiaki Saito

IPC分类号： H03K17/00

CPC分类号： H01L27/112 ,  H03K19/17736

摘要： A pass transistor circuit according to an embodiment includes: a first input/output terminal connected to a first signal line; a second input/output terminal connected to a second signal line; a first device having a first terminal connected to a first power supply and a second terminal; a second device having a third terminal connected to the second terminal and a fourth terminal connected to a second power supply; a first transistor having one of source/drain connected to the second terminal, a gate receiving a first control signal; and a second transistor having a gate connected to the other one of source/drain of the first transistor, one of source/drain connected to the first input/output terminal, and the other one of source/drain connected to the second input/output terminal. One of the first and second devices is a nonvolatile memory device, the other one of the first and second devices is a MOSFET.

摘要翻译： 根据实施例的传输晶体管电路包括：连接到第一信号线的第一输入/输出端子; 连接到第二信号线的第二输入/输出端子; 第一装置，具有连接到第一电源和第二端子的第一端子; 第二装置，具有连接到第二端子的第三端子和连接到第二电源的第四端子; 第一晶体管，其源极/漏极中的一个连接到第二端子，栅极接收第一控制信号; 以及第二晶体管，其栅极连接到第一晶体管的源极/漏极中的另一个，栅极/漏极中的一个连接到第一输入/输出端子，另一个源极/漏极连接到第二输入/输出端 终奌站。 第一和第二器件中的一个是非易失性存储器件，第一和第二器件中的另一个是MOSFET。

公开(公告)号：US08139403B2

公开(公告)日：2012-03-20

申请号：US12885833

申请日：2010-09-20

申请人： Tomoaki Inokuchi ,  Takao Marukame ,  Mizue Ishikawa ,  Hideyuki Sugiyama ,  Hisanori Aikawa ,  Masahiko Nakayama ,  Tatsuya Kishi ,  Hiroaki Yoda ,  Yoshiaki Saito

发明人： Tomoaki Inokuchi ,  Takao Marukame ,  Mizue Ishikawa ,  Hideyuki Sugiyama ,  Hisanori Aikawa ,  Masahiko Nakayama ,  Tatsuya Kishi ,  Hiroaki Yoda ,  Yoshiaki Saito

IPC分类号： G11C11/15 ,  G11C29/82

CPC分类号： H01L29/66984 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1677 ,  G11C11/1697 ,  H01L27/224 ,  H01L43/08

摘要： Certain embodiments provide a spin memory including a memory cell including a ferromagnetic stacked film that has a stacked structure in which a first ferromagnetic layer, a first nonmagnetic layer, a second ferromagnetic layer, a second nonmagnetic layer, and a third ferromagnetic layer are stacked in this order or reverse order, the third ferromagnetic layer and the second ferromagnetic layer being antiferromagnetically exchange-coupled via the second nonmagnetic layer. The ferromagnetic stacked film includes a current path in which a first and second write currents flow from the first ferromagnetic layer to the third ferromagnetic layer to write a first and second magnetization states into the first ferromagnetic layer respectively, and the second write current is higher than the first write current.

摘要翻译： 某些实施例提供一种自旋存储器，其包括一个存储单元，该存储单元包括一个具有层叠结构的铁磁层叠膜，其中第一铁磁层，第一非磁性层，第二铁磁层，第二非磁性层和第三铁磁层堆叠在其中 该顺序或反向顺序，第三铁磁层和第二铁磁层经由第二非磁性层反铁磁交换耦合。 铁磁层叠膜包括电流路径，其中第一和第二写入电流从第一铁磁层流向第三铁磁层，以将第一和第二磁化状态分别写入第一铁磁层，并且第二写入电流高于 第一次写入电流。

公开(公告)号：US20100019798A1

公开(公告)日：2010-01-28

申请号：US12486999

申请日：2009-06-18

申请人： Yoshiaki Saito ,  Hideyuki Sugiyama ,  Tomoaki Inokuchi ,  Mizue Ishikawa ,  Takao Marukame

发明人： Yoshiaki Saito ,  Hideyuki Sugiyama ,  Tomoaki Inokuchi ,  Mizue Ishikawa ,  Takao Marukame

IPC分类号： H03K19/0944 ,  H01L29/00

CPC分类号： H01L29/66984 ,  B82Y25/00 ,  H01F10/3272 ,  H01F10/3286

摘要： It is made possible to provide a spin MOSFET that can minimize the increase in production costs and can perform both spin injection writing and reading. A spin MOSFET includes: a substrate that has a semiconductor region of a first conductivity type; first and second ferromagnetic stacked films that are formed at a distance from each other on the semiconductor region, and each have the same stacked structure comprising a first ferromagnetic layer, a nonmagnetic layer, and a second ferromagnetic layer stacked in this order, the second ferromagnetic stacked film having a film-plane area different from that of the first ferromagnetic stacked film; a gate insulating film that is formed on a portion of the semiconductor region, the portion being located between the first ferromagnetic stacked film and the second ferromagnetic stacked film; and a gate that is formed on the gate insulating film.

摘要翻译： 可以提供一种可以使生产成本增加最小化的自旋MOSFET，并且可以执行自动注入写入和读取两种操作。 自旋MOSFET包括：具有第一导电类型的半导体区域的衬底; 第一和第二铁磁层叠膜，其形成在半导体区域上彼此间隔一定距离处，并且各自具有包括依次层叠的第一铁磁层，非磁性层和第二铁磁层的相同层叠结构，第二铁磁体 具有与第一铁磁性层叠膜不同的膜面积的层叠膜; 形成在所述半导体区域的一部分上的所述栅绝缘膜，所述栅极绝缘膜位于所述第一铁磁层叠膜和所述第二铁磁性堆叠膜之间; 以及形成在栅极绝缘膜上的栅极。

公开(公告)号：US08618590B2

公开(公告)日：2013-12-31

申请号：US12561475

申请日：2009-09-17

申请人： Tomoaki Inokuchi ,  Takao Marukame ,  Mizue Ishikawa ,  Hideyuki Sugiyama ,  Yoshiaki Saito

发明人： Tomoaki Inokuchi ,  Takao Marukame ,  Mizue Ishikawa ,  Hideyuki Sugiyama ,  Yoshiaki Saito

IPC分类号： H01L21/02 ,  G11C11/14

CPC分类号： H01L29/66984 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693

摘要： A spin transistor includes a first ferromagnetic layer, a second ferromagnetic layer, a semiconductor layer between the first and second ferromagnetic layers, and a gate electrode on or above a surface of the semiconductor layer, the surface being between the first and second ferromagnetic layers. The first ferromagnetic layer comprises a ferromagnet which has a first minority spin band located at a high energy side and a second minority spin band located at a low energy side, and has a Fermi level in an area of the high energy side higher than a middle of a gap between the first and second minority spin bands.

摘要翻译： 自旋晶体管包括第一铁磁层，第二铁磁层，第一和第二铁磁层之间的半导体层，以及在半导体层的表面上或上方的栅电极，该表面位于第一和第二铁磁层之间。 第一铁磁层包括具有位于高能侧的第一少数自旋带和位于低能侧的第二少数自旋带的铁磁体，并且在高能量侧的区域中的费米能级高于中间 第一和第二少数自旋带之间的间隙。

公开(公告)号：US08487359B2

公开(公告)日：2013-07-16

申请号：US12486999

申请日：2009-06-18

申请人： Yoshiaki Saito ,  Hideyuki Sugiyama ,  Tomoaki Inokuchi ,  Mizue Ishikawa ,  Takao Marukame

发明人： Yoshiaki Saito ,  Hideyuki Sugiyama ,  Tomoaki Inokuchi ,  Mizue Ishikawa ,  Takao Marukame

IPC分类号： H01L27/108

CPC分类号： H01L29/66984 ,  B82Y25/00 ,  H01F10/3272 ,  H01F10/3286

摘要： It is made possible to provide a spin MOSFET that can minimize the increase in production costs and can perform both spin injection writing and reading. A spin MOSFET includes: a substrate that has a semiconductor region of a first conductivity type; first and second ferromagnetic stacked films that are formed at a distance from each other on the semiconductor region, and each have the same stacked structure comprising a first ferromagnetic layer, a nonmagnetic layer, and a second ferromagnetic layer stacked in this order, the second ferromagnetic stacked film having a film-plane area different from that of the first ferromagnetic stacked film; a gate insulating film that is formed on a portion of the semiconductor region, the portion being located between the first ferromagnetic stacked film and the second ferromagnetic stacked film; and a gate that is formed on the gate insulating film.

摘要翻译： 可以提供一种可以使生产成本增加最小化的自旋MOSFET，并且可以执行自动注入写入和读取两种操作。 自旋MOSFET包括：具有第一导电类型的半导体区域的衬底; 第一和第二铁磁层叠膜，其形成在半导体区域上彼此间隔一定距离处，并且各自具有包括依次层叠的第一铁磁层，非磁性层和第二铁磁层的相同层叠结构，第二铁磁体 具有与第一铁磁性层叠膜不同的膜面积的层叠膜; 形成在所述半导体区域的一部分上的所述栅绝缘膜，所述栅极绝缘膜位于所述第一铁磁层叠膜和所述第二铁磁性堆叠膜之间; 以及形成在栅极绝缘膜上的栅极。

公开(公告)号：US08330196B2

公开(公告)日：2012-12-11

申请号：US13419947

申请日：2012-03-14

申请人： Takao Marukame ,  Mizue Ishikawa ,  Tomoaki Inokuchi ,  Hideyuki Sugiyama ,  Yoshiaki Saito

发明人： Takao Marukame ,  Mizue Ishikawa ,  Tomoaki Inokuchi ,  Hideyuki Sugiyama ,  Yoshiaki Saito

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/66984 ,  H01L21/823814 ,  H01L21/84 ,  H01L21/845 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/49 ,  H01L29/66075

摘要： A semiconductor device according to an embodiment includes: a semiconductor layer; source and drain regions in the semiconductor layer; a magnetic metal semiconductor compound film on each of the source and drain regions, the magnetic metal semiconductor compound film including the same semiconductor as a semiconductor of the semiconductor layer and a magnetic metal; a gate insulating film on the semiconductor layer between the source region and the drain region; a gate electrode on the gate insulating film; a gate sidewall formed at a side portion of the gate electrode, the gate sidewall being made of an insulating material; a film stack formed on the magnetic metal semiconductor compound film on each of the source and drain regions, the film stack including a magnetic layer; and an oxide layer formed on the gate sidewall, the oxide layer containing the same element as an element in the film stack.

摘要翻译： 根据实施例的半导体器件包括：半导体层; 半导体层中的源极和漏极区域; 在源极和漏极区域中的每一个上的磁性金属半导体化合物膜，包括与半导体层的半导体相同的半导体的磁性金属半导体化合物膜和磁性金属; 源极区域和漏极区域之间的半导体层上的栅极绝缘膜; 栅极绝缘膜上的栅电极; 栅极侧壁，其形成在所述栅电极的侧部，所述栅极侧壁由绝缘材料制成; 在所述源极和漏极区域中的每一个上形成在所述磁性金属半导体化合物膜上的膜堆叠，所述膜堆叠包括磁性层; 以及形成在栅极侧壁上的氧化物层，所述氧化物层包含与膜堆叠中的元件相同的元件。

公开(公告)号：US08154916B2

公开(公告)日：2012-04-10

申请号：US12889881

申请日：2010-09-24

申请人： Hideyuki Sugiyama ,  Tetsufumi Tanamoto ,  Takao Marukame ,  Mizue Ishikawa ,  Tomoaki Inokuchi ,  Yoshiaki Saito

发明人： Hideyuki Sugiyama ,  Tetsufumi Tanamoto ,  Takao Marukame ,  Mizue Ishikawa ,  Tomoaki Inokuchi ,  Yoshiaki Saito

IPC分类号： G11C11/14

CPC分类号： G11C14/0081

摘要： Certain embodiments provide a nonvolatile memory circuit in which a first p-channel MOS transistor and a first n-channel spin MOS transistor are connected in series, a second p-channel MOS transistor and a second n-channel spin MOS transistor are connected in series, gates of the first p-channel MOS transistor and the first n-channel spin MOS transistor are connected, gates of the second p-channel MOS transistor and the second n-channel spin MOS transistor are connected, a first n-channel transistor includes a drain connected to a drain of the first p-channel transistor and the gate of the second p-channel transistor, a second n-channel transistor includes a drain connected to a drain of the second p-channel transistor and the gate of the first p-channel transistor, and gates of the first and second n-channel transistors are connected.

摘要翻译： 某些实施例提供了其中第一p沟道MOS晶体管和第一n沟道自旋MOS晶体管串联连接的非易失性存储器电路，第二p沟道MOS晶体管和第二n沟道自旋MOS晶体管串联连接 第一p沟道MOS晶体管和第一n沟道自旋MOS晶体管的栅极连接，第二p沟道MOS晶体管和第二n沟道自旋MOS晶体管的栅极连接，第一n沟道晶体管包括 连接到第一p沟道晶体管的漏极和第二p沟道晶体管的栅极的漏极，第二n沟道晶体管包括连接到第二p沟道晶体管的漏极和第一p沟道晶体管的栅极的漏极 p沟道晶体管，第一和第二n沟道晶体管的栅极连接。