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    Semiconductor memory device having extended period for outputting data
    1.
    发明授权
    Semiconductor memory device having extended period for outputting data 失效
    具有用于输出数据的延长周期的半导体存储器件

    公开(公告)号：US4707811A

    公开(公告)日：1987-11-17

    申请号：US674313

    申请日：1984-11-23

    申请人： Yoshihiro Takemae ,  Tomio Nakano ,  Masao Nakano ,  Kimiaki Sato

    发明人： Yoshihiro Takemae ,  Tomio Nakano ,  Masao Nakano ,  Kimiaki Sato

    IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C8/00 ,  G11C8/04 ,  G11C8/18 ,  G11C11/409

    CPC分类号： G11C8/04 ,  G11C7/1024 ,  G11C7/1033 ,  G11C8/18

    摘要： A semiconductor memory device has an operational mode such as a nibble mode or page mode, a first address strobe signal is kept in an active state, and a second address strobe signal is successively switched between an active state and standby state, thereby enabling successive data output. Previous output data is reset once, in accordance with the switchover of the second address strobe signal to the active state while the first address strobe signal is in the active state, before outputting data, and the reset operation for outputting is also performed when both the first and second address strobe signals are switched to the standby state, so that the period in which the data is output is expanded.

    摘要翻译： 半导体存储器件具有诸如半字节模式或页面模式的操作模式，第一地址选通信号保持在活动状态，并且第二地址选通信号在活动状态和待机状态之间被连续切换，从而使能连续的数据 输出。 在输出数据之前，根据第二地址选通信号切换到激活状态的先前输出数据被复位一次，而在输出数据之前也执行用于输出的复位操作 第一和第二地址选通信号被切换到待机状态，从而扩展数据输出的周期。

    Integrated circuit device
    2.
    发明授权
    Integrated circuit device 失效
    集成电路器件

    公开(公告)号：US4903111A

    公开(公告)日：1990-02-20

    申请号：US265275

    申请日：1988-10-25

    申请人： Yoshihiro Takemae ,  Tomio Nakano ,  Masao Nakano ,  Kimiaki Sato

    发明人： Yoshihiro Takemae ,  Tomio Nakano ,  Masao Nakano ,  Kimiaki Sato

    IPC分类号： G11C17/14 ,  G11C17/16 ,  G11C29/00 ,  H01L23/525

    CPC分类号： G11C29/785 ,  G11C17/16 ,  H01L23/5256 ,  H01L2924/0002

    摘要： A semiconductor integrated circuit device having a fuse-blown type ROM for storing information concerning defective bits for the replacement of defective bits in a semiconductor memory device, etc., with redundant bits. The integrated circuit device comprises fuses for constituting the ROM, pads for supplying a melting current to the fuses, and PN junctions each being formed, for example, by a semiconductor substrate and a diffusion layer formed on the semiconductor substrate. Each of the fuses is melted by applying voltage to a circuit connecting the PN junction, the fuse, and the pad so that the PN junction is forward biased, thereby supplying a large current to the fuse.

    摘要翻译： 一种半导体集成电路器件，具有熔丝熔断型ROM，用于存储关于半导体存储器件等中的有缺陷的位的替换的缺陷位的信息等。 集成电路装置包括用于构成ROM的保险丝，用于向保险丝提供熔化电流的焊盘，以及例如由形成在半导体衬底上的半导体衬底和扩散层形成的PN结。 通过向连接PN结，熔丝和焊盘的电路施加电压来熔化每个保险丝，使得PN结正向偏置，从而向保险丝提供大电流。

    Semiconductor memory device having stacked-capacitor type memory cells
    4.
    发明授权
    Semiconductor memory device having stacked-capacitor type memory cells 失效
    具有堆叠电容器型存储单元的半导体存储器件

    公开(公告)号：US4754313A

    公开(公告)日：1988-06-28

    申请号：US93128

    申请日：1987-09-02

    申请人： Yoshihiro Takemae ,  Tomio Nakano ,  Masao Nakano ,  Kimiaki Sato

    发明人： Yoshihiro Takemae ,  Tomio Nakano ,  Masao Nakano ,  Kimiaki Sato

    IPC分类号： G11C11/401 ,  G11C11/404 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L27/02 ,  H01L29/04 ,  H01L29/78

    CPC分类号： G11C11/404 ,  H01L21/8221 ,  H01L27/10808

    摘要： A semiconductor memory device including: a substrate; a plurality of word lines; a plurality of bit lines; and a plurality of memory cells, each positioned at an intersection defined by one of the word lines and one of the bit lines and including a transfer transistor and a capacitor. Each of the memory cells has a first insulating layer covering a gate of the transfer transistor. The capacitor in each memory cell includes a second conductive layer which contacts one of source and drain regions of the transfer transistor in the memory cell, through the first insulating layer, and extends over the gate of the transfer transistor, a second insulating layer formed on the first conductive layer, and a second conductive layer extending over the second insulating layer. The semiconductor memory device further includes an additional conductive layer directly connected to the other of the source and drain regions of the transfer transistor in the memory cell, through the first insulating layer covering same, and extending over the gate of the adjoining transfer transistors. Each bit line is connected to the other of the source and drain regions through the additional conductive layer. A method for manufacturing a semiconductor memory device having the above construction.

    摘要翻译： 一种半导体存储器件，包括：衬底; 多个字线; 多个位线; 以及多个存储单元，每个存储单元位于由字线之一和一个位线限定的交点处，并且包括转移晶体管和电容器。 每个存储单元具有覆盖转移晶体管的栅极的第一绝缘层。 每个存储单元中的电容器包括第二导电层，其通过第一绝缘层接触存储单元中的转移晶体管的源区和漏区之一，并延伸在转移晶体管的栅极上，第二绝缘层形成在 第一导电层和在第二绝缘层上延伸的第二导电层。 半导体存储器件还包括通过覆盖其的第一绝缘层直接连接到存储单元中的传输晶体管的源极和漏极区域中的另一个的另外的导电层，并且在相邻的转移晶体管的栅极上延伸。 每个位线通过附加导电层连接到另一个源极和漏极区域。 一种具有上述结构的半导体存储器件的制造方法。

    Semiconductor memory device having a circuit for compensating for discriminating voltage of memory cells
    6.
    发明授权
    Semiconductor memory device having a circuit for compensating for discriminating voltage of memory cells 失效
    具有用于补偿存储单元的鉴别电压的电路的半导体存储器件

    公开(公告)号：US4716549A

    公开(公告)日：1987-12-29

    申请号：US901680

    申请日：1986-08-29

    申请人： Masao Nakano ,  Yoshihiro Takemae ,  Tomio Nakano ,  Shigeki Nozaki ,  Kimiaki Sato ,  Nobumi Kodama

    发明人： Masao Nakano ,  Yoshihiro Takemae ,  Tomio Nakano ,  Shigeki Nozaki ,  Kimiaki Sato ,  Nobumi Kodama

    IPC分类号： G11C11/407 ,  G11C11/40 ,  G11C11/409 ,  G11C11/4094 ,  G11C11/4099 ,  G11C7/02 ,  G11C11/24

    CPC分类号： G11C11/4099 ,  G11C11/4094

    摘要： A semiconductor memory device capable of compensating for variation in a discriminating voltage of a memory cell comprising a memory cell and a gate circuit for coupling the memory cell to a bit line. The device has a precharge circuit for precharging the bit line pair to a predetermined resultant precharge voltage in a reset state. The precharge circuit precharges a bit line pair with the resultant precharge voltage obtained by adding a compensating voltage to a precharge voltage in the reset state. The compensating voltage is adapted to compensate for variation in a memory cell discriminating voltage based on variation in a memory cell voltage caused by capacitive coupling of a word line to a memory capacitor due to a parasitic capacitance of a gate circuit in the active state, and the precharge voltage is adapted to optimize the memory cell discriminating voltage when it is assumed that the parasitic capacitance is not present.

    摘要翻译： 一种半导体存储器件，其能够补偿包括存储单元的存储单元和用于将存储单元耦合到位线的门电路的识别电压的变化。 该装置具有用于在复位状态下将位线对预充电到预定的合成预充电电压的预充电电路。 预充电电路对通过在复位状态下将补偿电压加到预充电电压而获得的所得预充电电压对位线对进行预充电。 补偿电压适于基于由于处于活动状态的栅极电路的寄生电容而由字线与存储电容器的电容耦合而引起的存储单元电压的变化来补偿存储单元识别电压的变化，以及 当假设寄生电容不存在时，预充电电压适于优化存储单元识别电压。

    Dynamic semiconductor memory device
    8.
    发明授权
    Dynamic semiconductor memory device 失效
    动态半导体存储器件

    公开(公告)号：US4597059A

    公开(公告)日：1986-06-24

    申请号：US535987

    申请日：1983-09-26

    申请人： Yoshihiro Takemae ,  Tomio Nakano ,  Kimiaki Sato

    发明人： Yoshihiro Takemae ,  Tomio Nakano ,  Kimiaki Sato

    IPC分类号： G11C11/407 ,  G11C8/14 ,  G11C11/408 ,  G11C7/00

    CPC分类号： G11C11/4085 ,  G11C8/14

    摘要： A dynamic semiconductor memory device comprising: (1) one-transistor one-capacitor type memory cells connected between word lines and bit lines and (2) flip-flops, each flip-flop being connected between a pair of word lines to clamp an unselected word line in the pair of word lines to the low voltage of a power source, thereby preventing a subsequent erroneous reading operation as a result of an increase in potential of the unselected word line.

    摘要翻译： 一种动态半导体存储器件，包括：（1）连接在字线和位线之间的单晶体管单电容型存储单元，以及（2）触发器，每个触发器连接在一对字线之间以钳位未选择的 在一对字线中的字线到电源的低电压，从而防止作为未选择字线的电位增加的结果的随后的错误读取操作。

    Dynamic semiconductor memory device
    9.
    发明授权
    Dynamic semiconductor memory device 失效
    动态半导体存储器件

    公开(公告)号：US4578776A

    公开(公告)日：1986-03-25

    申请号：US555891

    申请日：1983-11-28

    申请人： Yoshihiro Takemae ,  Tomio Nakano ,  Kimiaki Sato

    发明人： Yoshihiro Takemae ,  Tomio Nakano ,  Kimiaki Sato

    IPC分类号： G11C11/404 ,  G11C11/4074 ,  G11C11/24

    CPC分类号： G11C11/4074

    摘要： A dynamic semiconductor memory device includes a one-transistor one-capacitor type dynamic memory cell and a voltage dividing circuit having a potential providing terminal for providing an intermediate potential between the potential of the power supply and ground potential. One electrode of the capacitor in the memory cell is connected to the potential providing terminal. The voltage dividing circuit includes a potential switching circuit which changes the intermediate potential synchronously with an internal clock signal for selecting a word line, thus preventing a read error.

    摘要翻译： 动态半导体存储器件包括单晶体管单电容型动态存储单元和分压电路，其具有用于在电源的电位和地电位之间提供中间电位的电位提供端。 存储单元中的电容器的一个电极连接到电位提供端子。 分压电路包括电位切换电路，其与用于选择字线的内部时钟信号同步地改变中间电位，从而防止读取错误。

    Semiconductor memory device having stacked capacitor-type memory cells
    10.
    发明授权
    Semiconductor memory device having stacked capacitor-type memory cells 失效
    具有层叠电容器型存储单元的半导体存储器件

    公开(公告)号：US4641166A

    公开(公告)日：1987-02-03

    申请号：US560171

    申请日：1983-12-12

    申请人： Yoshihiro Takemae ,  Tomio Nakano ,  Kimiaki Sato

    发明人： Yoshihiro Takemae ,  Tomio Nakano ,  Kimiaki Sato

    IPC分类号： G11C11/401 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78

    CPC分类号： H01L27/10808

    摘要： In a semiconductor memory device having stacked capacitor-type memory cells, the capacitor of each memory cell comprises an electrode, an insulating layer, and a counter electrode. The electrode is connected electrically to a source or drain region of a transfer transistor and extends over a part of a word line adjacent to another word line serving a gate electrode of the transfer transistor, at which part no memory cell is formed.

    摘要翻译： 在具有层叠电容器型存储单元的半导体存储器件中，每个存储单元的电容器包括电极，绝缘层和对电极。 电极电连接到转移晶体管的源极或漏极区域，并且延伸到与传送晶体管的栅电极相连的另一个字线相邻的字线的一部分上，在该部分没有形成存储单元。