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公开(公告)号：US08441036B2
公开(公告)日：2013-05-14
申请号：US11724389
申请日：2007-03-15
IPC分类号： H01L29/739
CPC分类号： H01L29/7828 , H01L21/0273 , H01L21/32139 , H01L29/1608 , H01L29/267 , H01L29/4236 , H01L29/66068
摘要： A trench is formed extending from a surface of a hetero semiconductor region of a polycrystal silicon to the drain region. Further, a driving point of the field effect transistor, where a gate insulating film, the hetero semiconductor region and the drain region are adjoined, is formed at a position spaced apart from a side wall of the trench.
摘要翻译： 形成从多晶硅的异质半导体区域的表面延伸到漏极区域的沟槽。 此外，栅极绝缘膜，异质半导体区域和漏极区域相邻的场效应晶体管的驱动点形成在与沟槽的侧壁间隔开的位置处。
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2.发明授权Semiconductor device with hetero semiconductor region and method of manufacturing the same 有权具有异质半导体区域的半导体器件及其制造方法公开(公告)号：US08164116B2
公开(公告)日：2012-04-24
申请号：US12065847
申请日：2006-08-22
IPC分类号： H01L29/66
CPC分类号： H01L29/861 , H01L21/046 , H01L29/0623 , H01L29/0653 , H01L29/1608 , H01L29/267 , H01L29/6606 , H01L29/66068 , H01L29/7828
摘要： A semiconductor device includes: a semiconductor base; a hetero semiconductor region which is in contact with the semiconductor base and which has a band gap different from that of the semiconductor base; a first electrode connected to the hetero semiconductor region; and a second electrode forming an ohmic contact to the semiconductor base. The hetero semiconductor region includes a laminated hetero semiconductor region formed by laminating a plurality of semiconductor layers in which crystal alignment is discontinuous at a boundary between at least two layers.
摘要翻译： 半导体器件包括：半导体基底; 与半导体基底接触并且具有与半导体基底不同的带隙的异质半导体区域; 连接到所述异质半导体区域的第一电极; 以及形成与半导体基底的欧姆接触的第二电极。 异质半导体区域包括通过层叠在至少两层之间的边界处晶体取向不连续的多个半导体层而形成的层叠异质半导体区域。
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公开(公告)号：US20110117699A1
公开(公告)日：2011-05-19
申请号：US13014190
申请日：2011-01-26
IPC分类号： H01L21/336 , H01L21/04
CPC分类号： H01L29/7828 , H01L29/0623 , H01L29/1608 , H01L29/267 , H01L29/66068
摘要： A semiconductor substrate made of a semiconductor material is prepared, and a hetero semiconductor region is formed on the semiconductor substrate to form a heterojunction in an interface between the hetero semiconductor region and the semiconductor substrate. The hetero semiconductor region is made of a semiconductor material having a bandgap different from that of the semiconductor material, and a part of the hetero semiconductor region includes a film thickness control portion whose film thickness is thinner than that of the other part thereof. By oxidizing the hetero semiconductor region with a thickness equal to the film thickness of the film thickness control portion, a gate insulating film adjacent to the heterojunction is formed. A gate electrode is formed on the gate insulating film. This makes it possible to manufacture a semiconductor device including the gate insulating film with a lower ON resistance, and with a higher insulating characteristic and reliability.
摘要翻译： 制备由半导体材料制成的半导体衬底，并且在半导体衬底上形成异质半导体区域，以在异质半导体区域和半导体衬底之间的界面中形成异质结。 异质半导体区域由具有与半导体材料的带隙不同的带隙的半导体材料制成，并且异质半导体区域的一部分包括膜厚度比其他部分薄的膜厚控制部分。 通过以等于膜厚控制部分的膜厚的厚度氧化杂半导体区域，形成与异质结相邻的栅极绝缘膜。 在栅极绝缘膜上形成栅电极。 这使得可以制造包括具有较低导通电阻的栅极绝缘膜以及更高的绝缘特性和可靠性的半导体器件。
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公开(公告)号：US07902025B2
公开(公告)日：2011-03-08
申请号：US11773649
申请日：2007-07-05
IPC分类号： H01L21/336
CPC分类号： H01L29/7828 , H01L29/0623 , H01L29/1608 , H01L29/267 , H01L29/66068
摘要： A semiconductor substrate made of a semiconductor material is prepared, and a hetero semiconductor region is formed on the semiconductor substrate to form a heterojunction in an interface between the hetero semiconductor region and the semiconductor substrate. The hetero semiconductor region is made of a semiconductor material having a bandgap different from that of the semiconductor material, and a part of the hetero semiconductor region includes a film thickness control portion whose film thickness is thinner than that of the other part thereof. By oxidizing the hetero semiconductor region with a thickness equal to the film thickness of the film thickness control portion, a gate insulating film adjacent to the heterojunction is formed. A gate electrode is formed on the gate insulating film. This makes it possible to manufacture a semiconductor device including the gate insulating film with a lower ON resistance, and with a higher insulating characteristic and reliability.
摘要翻译： 制备由半导体材料制成的半导体衬底，并且在半导体衬底上形成异质半导体区域，以在异质半导体区域和半导体衬底之间的界面中形成异质结。 异质半导体区域由具有与半导体材料的带隙不同的带隙的半导体材料制成，并且异质半导体区域的一部分包括膜厚度比其他部分薄的膜厚控制部分。 通过以等于膜厚控制部分的膜厚的厚度氧化杂半导体区域，形成与异质结相邻的栅极绝缘膜。 在栅极绝缘膜上形成栅电极。 这使得可以制造包括具有较低导通电阻的栅极绝缘膜以及更高的绝缘特性和可靠性的半导体器件。
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公开(公告)号：US07588961B2
公开(公告)日：2009-09-15
申请号：US11377909
申请日：2006-03-16
IPC分类号： H01L21/00
CPC分类号： H01L29/78 , H01L21/047 , H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/772 , H01L29/7828
摘要： In general, this disclosure describes a semiconductor device that exhibits an increased resistance and reduced leakage current in a reverse-biased state, and a method for manufacturing such a semiconductor device. For example, in one embodiment, the increased resistance in the reverse-biased state is obtained by introducing either a P+ or P− type impurity in a polycrystalline silicon layer formed on an N− type epitaxial layer. Additionally, the semiconductor device maintains a low resistance in a forward-biased state. To keep the forward-biased resistance low, the polycrystalline silicon layer in the vicinity of a gate electrode may be of an N+ type. Furthermore, an N+ type source extracting region is formed on the surface of the polycrystalline silicon layer to connect a source electrode to a drain electrode and maintain a low resistance when forward-biased.
摘要翻译： 通常，本公开描述了在反向偏置状态下呈现增加的电阻和减小的漏电流的半导体器件，以及用于制造这种半导体器件的方法。 例如，在一个实施例中，通过在形成在N型外延层上的多晶硅层中引入P +或P-型杂质来获得反向偏置状态下的增加的电阻。 此外，半导体器件在正向偏置状态下保持低电阻。 为了使正向偏置电阻低，在栅电极附近的多晶硅层可以是N +型。 此外，在多晶硅层的表面上形成N +型源极提取区域，以将源电极连接到漏电极，并且当正向偏置时保持低电阻。
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公开(公告)号：US20070235745A1
公开(公告)日：2007-10-11
申请号：US11783577
申请日：2007-04-10
IPC分类号： H01L33/00 , H01L29/861 , H01L29/80
CPC分类号： H01L29/7808 , H01L29/0619 , H01L29/1608 , H01L29/165 , H01L29/6606 , H01L29/7802 , H01L29/7811 , H01L29/7828 , H01L29/8083 , H01L29/861 , H01L29/8618 , H01L29/872
摘要： Impurity concentration of a second semiconductor region is set such that when a predetermined reverse bias is applied to a heterojunction diode configured by a first semiconductor region and the second semiconductor region, a breakdown voltage at least in a heterojunction region other than outer peripheral ends of the heterojunction diode is a breakdown voltage of a semiconductor device.
摘要翻译： 设定第二半导体区域的杂质浓度，使得当将预定的反向偏压施加到由第一半导体区域和第二半导体区域构成的异质结二极管时，至少在异种结区以外的击穿电压 异质结二极管是半导体器件的击穿电压。
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公开(公告)号：US20070210330A1
公开(公告)日：2007-09-13
申请号：US11714214
申请日：2007-03-06
IPC分类号： H01L29/732 , H01L21/8234
CPC分类号： H01L29/267 , H01L21/0475 , H01L29/0623 , H01L29/0847 , H01L29/1608 , H01L29/4236 , H01L29/66068 , H01L29/7828
摘要： A semiconductor device, includes: a first conductivity type semiconductor base having a main face; a hetero semiconductor region contacting the main face of the semiconductor base and forming a hetero junction in combination with the semiconductor base, the semiconductor base and the hetero semiconductor region in combination defining a junction end part; a gate insulating film defining a junction face in contact with the semiconductor base and having a thickness; and a gate electrode disposed adjacent to the junction end part via the gate insulating film and defining a shortest point in a position away from the junction end part by a shortest interval, a line extending from the shortest point to a contact point vertically relative to the junction face, forming such a distance between the contact point and the junction end part as to be smaller than the thickness of the gate insulating film contacting the semiconductor base.
摘要翻译： 一种半导体器件，包括：具有主面的第一导电型半导体基底; 与半导体基板的主面接触并与半导体基底结合形成异质结的异质半导体区域，半导体基底和异质半导体区域组合形成连接端部; 限定与半导体基底接触并具有厚度的接合面的栅极绝缘膜; 以及栅电极，其经由所述栅极绝缘膜与所述接合端部相邻设置，并且在远离所述接合端部的位置中以最短间隔限定最短点，从所述最短点到接触点相对于所述接合端垂直延伸的线 接合面在接触点和接合端部之间形成的距离小于与半导体基底接触的栅极绝缘膜的厚度。
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公开(公告)号：US07989295B2
公开(公告)日：2011-08-02
申请号：US13014190
申请日：2011-01-26
IPC分类号： H01L21/336
CPC分类号： H01L29/7828 , H01L29/0623 , H01L29/1608 , H01L29/267 , H01L29/66068
摘要： A semiconductor substrate made of a semiconductor material is prepared, and a hetero semiconductor region is formed on the semiconductor substrate to form a heterojunction in an interface between the hetero semiconductor region and the semiconductor substrate. The hetero semiconductor region is made of a semiconductor material having a bandgap different from that of the semiconductor material, and a part of the hetero semiconductor region includes a film thickness control portion whose film thickness is thinner than that of the other part thereof. By oxidizing the hetero semiconductor region with a thickness equal to the film thickness of the film thickness control portion, a gate insulating film adjacent to the heterojunction is formed. A gate electrode is formed on the gate insulating film. This makes it possible to manufacture a semiconductor device including the gate insulating film with a lower ON resistance, and with a higher insulating characteristic and reliability.
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公开(公告)号：US07671383B2
公开(公告)日：2010-03-02
申请号：US11714214
申请日：2007-03-06
IPC分类号： H01L29/732
CPC分类号： H01L29/267 , H01L21/0475 , H01L29/0623 , H01L29/0847 , H01L29/1608 , H01L29/4236 , H01L29/66068 , H01L29/7828
摘要： A semiconductor device, includes: a first conductivity type semiconductor base having a main face; a hetero semiconductor region contacting the main face of the semiconductor base and forming a hetero junction in combination with the semiconductor base, the semiconductor base and the hetero semiconductor region in combination defining a junction end part; a gate insulating film defining a junction face in contact with the semiconductor base and having a thickness; and a gate electrode disposed adjacent to the junction end part via the gate insulating film and defining a shortest point in a position away from the junction end part by a shortest interval, a line extending from the shortest point to a contact point vertically relative to the junction face, forming such a distance between the contact point and the junction end part as to be smaller than the thickness of the gate insulating film contacting the semiconductor base.
摘要翻译： 一种半导体器件，包括：具有主面的第一导电型半导体基底; 与半导体基板的主面接触并与半导体基底结合形成异质结的异质半导体区域，半导体基底和异质半导体区域组合形成连接端部; 限定与半导体基底接触并具有厚度的接合面的栅极绝缘膜; 以及栅电极，其经由所述栅极绝缘膜与所述接合端部相邻设置，并且在远离所述接合端部的位置中以最短间隔限定最短点，从所述最短点到接触点相对于所述接合端垂直延伸的线 接合面在接触点和接合端部之间形成的距离小于与半导体基底接触的栅极绝缘膜的厚度。
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公开(公告)号：US20090278169A1
公开(公告)日：2009-11-12
申请号：US12065847
申请日：2006-08-22
CPC分类号： H01L29/861 , H01L21/046 , H01L29/0623 , H01L29/0653 , H01L29/1608 , H01L29/267 , H01L29/6606 , H01L29/66068 , H01L29/7828
摘要： A semiconductor device includes: a semiconductor base; a hetero semiconductor region which is in contact with the semiconductor base and which has a band gap different from that of the semiconductor base; a first electrode connected to the hetero semiconductor region; and a second electrode forming an ohmic contact to the semiconductor base. The hetero semiconductor region includes a laminated hetero semiconductor region formed by laminating a plurality of semiconductor layers in which crystal alignment is discontinuous at a boundary between at least two layers.
摘要翻译： 半导体器件包括：半导体基底; 与半导体基底接触并且具有与半导体基底不同的带隙的异质半导体区域; 连接到所述异质半导体区域的第一电极; 以及形成与半导体基底的欧姆接触的第二电极。 异质半导体区域包括通过层叠在至少两层之间的边界处晶体取向不连续的多个半导体层而形成的层叠异质半导体区域。
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