公开(公告)号：US20120127814A1

公开(公告)日：2012-05-24

申请号：US13302772

申请日：2011-11-22

申请人： Yoshiro RIHO ,  Hiromasa NODA ,  Kazuki SAKUMA

发明人： Yoshiro RIHO ,  Hiromasa NODA ,  Kazuki SAKUMA

IPC分类号： G11C29/00

CPC分类号： G11C29/00 ,  G11C29/02 ,  G11C29/06 ,  G11C29/12005 ,  G11C29/28 ,  G11C29/50 ,  G11C2029/1202 ,  G11C2029/2602

摘要： A semiconductor device includes a memory cell array that is divided into a plurality of memory cell mats by a plurality of sense amplifier arrays. Each of the plurality of memory cell mats includes a plurality of word lines and a test circuit for performing a test control to activate, at one time, a plurality of word lines included in each of a plurality of selected memory cell mats that are not disposed adjacent each other in the plurality of memory cell mats. The memory cell mats with the plurality of activated word lines are distributed. Therefore, the load applied to a driver circuit for driving word lines and the load applied to a power supply circuit for supplying an operation voltage to the driver circuit are reduced

摘要翻译： 半导体器件包括由多个读出放大器阵列分成多个存储单元阵列的存储单元阵列。 多个存储单元垫中的每一个包括多个字线和用于执行测试控制的测试电路，以一次激活多个选定的未设置的存储单元垫中的每一个字线 在多个存储单元垫中彼此相邻。 分配具有多个激活字线的存储单元垫。 因此，施加到用于驱动字线的驱动电路的负载和施加到用于向驱动器电路提供工作电压的电源电路的负载减小

公开(公告)号：US20120133399A1

公开(公告)日：2012-05-31

申请号：US13306560

申请日：2011-11-29

申请人： Yuko WATANABE ,  Yoshiro RIHO ,  Hiromasa NODA ,  Yoji IDEI ,  Kosuke GOTO

发明人： Yuko WATANABE ,  Yoshiro RIHO ,  Hiromasa NODA ,  Yoji IDEI ,  Kosuke GOTO

IPC分类号： H03K3/00

CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C7/08 ,  G11C7/222 ,  G11C11/4074 ,  G11C11/4076

摘要： A semiconductor device includes a first driver circuit for supplying a first potential to a first power supply node of the sense amplifier, second and third driver circuits for supplying a second potential and a third potential to a second power supply node of the sense amplifier, and a timing control circuit for controlling operations of the first to third driver circuits. The timing control circuit includes a delay circuit for deciding an ON period of the third driver circuit. The delay circuit includes a first delay circuit having a delay amount that depends on an external power supply potential and a second delay circuit having a delay amount that does not depend on the external power supply potential, and the ON period of the third driver circuit is decided based on a sum of the delay amounts of the first and second delay circuits.

摘要翻译： 半导体器件包括用于向读出放大器的第一电源节点提供第一电位的第一驱动器电路，用于向读出放大器的第二电源节点提供第二电位和第三电位的第二和第三驱动器电路，以及 用于控制第一至第三驱动器电路的操作的定时控制电路。 定时控制电路包括用于决定第三驱动电路的接通时间的延迟电路。 延迟电路包括具有取决于外部电源电位的延迟量的第一延迟电路和具有不依赖于外部电源电位的延迟量的第二延迟电路，并且第三驱动电路的导通周期为 基于第一和第二延迟电路的延迟量的总和来决定。

公开(公告)号：US20110131440A1

公开(公告)日：2011-06-02

申请号：US12955635

申请日：2010-11-29

申请人： Hiromasa NODA

发明人： Hiromasa NODA

IPC分类号： G06F13/42 ,  H03K19/00

CPC分类号： H03K5/135 ,  H03K5/133 ,  H03K5/15 ,  H03K2005/0011

摘要： A semiconductor device includes an analog circuit with a first delay variation in response to a variation in a power supply potential, and a digital circuit with a second delay variation smaller than the first delay variation. The analog circuit is connected to a first power supply potential. The digital circuit includes a detecting circuit detecting a first delay caused by a first circuit connected to the first power supply potential, and a second circuit generating a control signal to control the analog circuit, the second circuit being connected to a second power supply potential whose potential variation is smaller than the first power supply potential. A second delay caused by the second circuit is controlled in correlation to the first delay.

摘要翻译： 半导体器件包括响应于电源电位变化的第一延迟变化的模拟电路和具有小于第一延迟变化的第二延迟变化的数字电路。 模拟电路连接到第一电源电位。 数字电路包括检测电路，检测由连接到第一电源电位的第一电路引起的第一延迟，以及产生控制信号以控制模拟电路的第二电路，第二电路连接到第二电源电位， 电位变化小于第一电源电位。 与第一延迟相关地控制由第二电路引起的第二延迟。

公开(公告)号：US20120307583A1

公开(公告)日：2012-12-06

申请号：US13586526

申请日：2012-08-15

申请人： Tetsuaki OKAHIRO ,  Hiromasa NODA ,  Katsunobu NOGUCHI

发明人： Tetsuaki OKAHIRO ,  Hiromasa NODA ,  Katsunobu NOGUCHI

IPC分类号： G11C7/00

CPC分类号： G11C11/408 ,  G11C11/406 ,  G11C16/3418 ,  G11C29/783

摘要： A semiconductor device according to the present invention has an address scrambling circuit for performing address scrambling operation of an address and a redundancy judging circuit for judging that redundancy judgment is performed about the address scrambled by the address scrambling circuit. This structure makes it possible to completely refresh operation concerned with normal word lines and redundancy word lines.

摘要翻译： 根据本发明的半导体器件具有用于执行地址的地址加扰操作的地址加扰电路和用于判断对由地址加扰电路加扰的地址执行冗余判断的冗余判定电路。 该结构使得可以完全刷新与正常字线和冗余字线有关的操作。

公开(公告)号：US20110273948A1

公开(公告)日：2011-11-10

申请号：US13168804

申请日：2011-06-24

申请人： Tetsuaki OKAHIRO ,  Hiromasa NODA ,  Katsunobu NOGUCHI

发明人： Tetsuaki OKAHIRO ,  Hiromasa NODA ,  Katsunobu NOGUCHI

IPC分类号： G11C11/402

CPC分类号： G11C11/408 ,  G11C11/406 ,  G11C16/3418 ,  G11C29/783

摘要： A semiconductor device according to the present invention has an address scrambling circuit for performing address scrambling operation of an address and a redundancy judging circuit for judging that redundancy judgment is performed about the address scrambled by the address scrambling circuit. This structure makes it possible to completely refresh operation concerned with normal word lines and redundancy word lines.

摘要翻译： 根据本发明的半导体器件具有用于执行地址的地址加扰操作的地址加扰电路和用于判断对由地址加扰电路加扰的地址执行冗余判断的冗余判定电路。 该结构使得可以完全刷新与正常字线和冗余字线有关的操作。

公开(公告)号：US20100034004A1

公开(公告)日：2010-02-11

申请号：US12537639

申请日：2009-08-07

申请人： Tetsuaki OKAHIRO ,  Hiromasa NODA

发明人： Tetsuaki OKAHIRO ,  Hiromasa NODA

IPC分类号： G11C5/02 ,  G11C7/02 ,  G11C5/06

CPC分类号： G11C11/4097 ,  G11C11/4099 ,  G11C11/413

摘要： There is provided a semiconductor memory device that includes: a plurality of memory mats each including a plurality of word lines, a plurality of bit lines, a plurality of memory cells each located at an intersection between the word line and the bit line, and at least one dummy word line not having connection to a dummy cell; a plurality of sense amplifier arrays located between adjacent memory mats, the sense amplifier arrays including a plurality of sense amplifiers including a pair of input/output nodes, one of which pair is connected to the bit lines of the adjacent memory mats on one side and the other of which pair is connected to the bit lines of the adjacent memory mats on the other side, respectively; and an activating unit which, in response to activation of the word line in a memory mat selected from the memory mats, activates the dummy word line in the memory mat adjacent to the selected memory mat.

摘要翻译： 提供了一种半导体存储器件，其包括：多个存储器衬垫，每个存储器衬垫包括多个字线，多个位线，多个存储器单元，每个存储单元分别位于字线和位线之间的交点处，并且在 至少一个没有连接到虚拟单元的虚拟字线; 位于相邻存储器垫之间的多个读出放大器阵列，所述读出放大器阵列包括多个读出放大器，所述多个读出放大器包括一对输入/输出节点，其中一个输出/输出节点对在一侧连接到相邻存储器阵列的位线， 另一个对分别连接到另一侧的相邻存储器垫的位线; 以及激活单元，响应于从存储器垫选择的存储器垫中的字线的激活，激活与所选存储器垫相邻的存储器垫中的虚拟字线。

公开(公告)号：US20110239062A1

公开(公告)日：2011-09-29

申请号：US13071121

申请日：2011-03-24

申请人： Hiromasa NODA

发明人： Hiromasa NODA

IPC分类号： G11C29/04 ,  G06F11/22

CPC分类号： G11C29/48 ,  G01R31/2884 ,  G11C29/1201

摘要： A semiconductor device includes a decoder, a first register unit, and a second register unit. The decoder generates first and second register control signals in response to an external test code signal. The first register unit is coupled to the decoder. The first register unit receives the first register control signal from the decoder. The first register unit outputs in series a plurality of test signals in response to the first register control signal. The second register unit is coupled to the first register unit. The second register unit receives the first and second register control signals from the decoder. The second register unit receives in series the plurality of test signals from the first register unit in response to the first register control signal. The second register unit outputs in parallel the plurality of test signals in response to the second register control signal.

摘要翻译： 半导体器件包括解码器，第一寄存器单元和第二寄存器单元。 解码器响应于外部测试码信号而产生第一和第二寄存器控制信号。 第一寄存器单元耦合到解码器。 第一寄存器单元从解码器接收第一寄存器控制信号。 第一寄存器单元响应于第一寄存器控制信号串行输出多个测试信号。 第二寄存器单元耦合到第一寄存器单元。 第二寄存器单元从解码器接收第一和第二寄存器控制信号。 第二寄存器单元响应于第一寄存器控制信号串行地接收来自第一寄存器单元的多个测试信号。 第二寄存器单元响应于第二寄存器控制信号并行地输出多个测试信号。

公开(公告)号：US20110222362A1

公开(公告)日：2011-09-15

申请号：US13112706

申请日：2011-05-20

申请人： Hiromasa NODA

发明人： Hiromasa NODA

IPC分类号： G11C5/14

CPC分类号： G11C29/02 ,  G11C7/1045 ,  G11C11/4074 ,  G11C11/408 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50008 ,  G11C2207/2227

摘要： A semiconductor memory device includes a row control circuit block and a column control circuit block each performing an access control over a memory cell array, a data I/O circuit block transmitting and receiving data to and from the memory cell array, and a control circuit changing at least a part of the row control circuit block, the column control circuit block, and the data I/O circuit block from a standby state into an active state in response to a setting of a predetermined mode signal to a mode register. According to the present invention, even if it is necessary to turn predetermined circuit blocks into the active state by an operation other than a read or write operation, there is no need to always set these circuit blocks into the active state.

摘要翻译： 半导体存储器件包括行控制电路块和列控制电路块，每个行控制电路块执行存储单元阵列上的访问控制，数据I / O电路块向存储单元阵列发送数据和从存储单元阵列接收数据;以及控制电路 响应于将预定模式信号设置到模式寄存器，将行控制电路块，列控制电路块和数据I / O电路块的至少一部分改变为从待机状态变为有效状态。 根据本发明，即使需要通过除了读取或写入操作之外的操作将预定的电路块转变为活动状态，也不需要总是将这些电路块设置为活动状态。

公开(公告)号：US20110026290A1

公开(公告)日：2011-02-03

申请号：US12848443

申请日：2010-08-02

申请人： Hiromasa NODA ,  Yasuji KOSHIKAWA

发明人： Hiromasa NODA ,  Yasuji KOSHIKAWA

IPC分类号： G11C5/02 ,  G11C7/06

CPC分类号： G11C5/02 ,  G11C5/025 ,  G11C8/10 ,  G11C11/4097

摘要： A semiconductor device includes a plurality of memory mats arranged in an X direction and a mat selecting circuit that activates a part of the memory mats based on a row address and maintains the rest of the memory mats inactivated. The memory mats are divided into a plurality of memory mat groups each including the same number of memory mats arranged in the X direction. The mat selecting circuit activates at least one of the memory mats included in each of the memory mat groups, while maintaining the rest of memory mats inactivated. With this operation, a portion of discontinuity does not occur in the memory mats arranged in the X direction, and thus the necessity of arranging two sub-word driver areas in the portion of discontinuity is eliminated.

摘要翻译： 半导体器件包括沿X方向布置的多个存储器垫，以及基于行地址激活存储器垫的一部分并且保持其余的存储器衬垫不被激活的衬垫选择电路。 存储器垫被分成多个存储器垫组，每个存储器垫组包括沿X方向布置的相同数量的存储器垫。 垫选择电路激活包括在每个存储器垫组中的至少一个存储器垫，同时保持其余的存储器垫不被激活。 通过这种操作，在X方向上排列的存储垫中不会发生一部分不连续性，因此消除了在不连续部分中布置两个子字驱动器区域的必要性。

公开(公告)号：US20140104916A1

公开(公告)日：2014-04-17

申请号：US14105280

申请日：2013-12-13

申请人： Hiromasa NODA ,  Yasuji KOSHIKAWA

发明人： Hiromasa NODA ,  Yasuji KOSHIKAWA

IPC分类号： G11C5/02

CPC分类号： G11C5/02 ,  G11C5/025 ,  G11C8/10 ,  G11C11/4097

摘要： A semiconductor device includes a plurality of memory mats arranged in an X direction and a mat selecting circuit that activates a part of the memory mats based on a row address and maintains the rest of the memory mats inactivated. The memory mats are divided into a plurality of memory mat groups each including the same number of memory mats arranged in the X direction. The mat selecting circuit activates at least one of the memory mats included in each of the memory mat groups, while maintaining the rest of memory mats inactivated. With this operation, a portion of discontinuity does not occur in the memory mats arranged in the X direction, and thus the necessity of arranging two sub-word driver areas in the portion of discontinuity is eliminated.

摘要翻译： 半导体器件包括沿X方向布置的多个存储器垫，以及基于行地址激活存储器垫的一部分并且保持其余的存储器衬垫不被激活的衬垫选择电路。 存储器垫被分成多个存储器垫组，每个存储器垫组包括沿X方向布置的相同数量的存储器垫。 垫选择电路激活包括在每个存储器垫组中的至少一个存储器垫，同时保持其余的存储器垫不被激活。 通过这种操作，在X方向上排列的存储垫中不会发生一部分不连续性，因此消除了在不连续部分中布置两个子字驱动器区域的必要性。