公开(公告)号：US08405145B2

公开(公告)日：2013-03-26

申请号：US13153348

申请日：2011-06-03

申请人： Hitoshi Matsuura ,  Yoshito Nakazawa ,  Tsuyoshi Kachi ,  Yuji Yatsuda

发明人： Hitoshi Matsuura ,  Yoshito Nakazawa ,  Tsuyoshi Kachi ,  Yuji Yatsuda

IPC分类号： H01L27/108 ,  H01L29/78

CPC分类号： H01L27/0629 ,  H01L21/26586 ,  H01L21/76897 ,  H01L29/0615 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8725

摘要： A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.

公开(公告)号：US07759730B2

公开(公告)日：2010-07-20

申请号：US12463962

申请日：2009-05-11

申请人： Hitoshi Matsuura ,  Yoshito Nakazawa ,  Tsuyoshi Kachi ,  Yuji Yatsuda

发明人： Hitoshi Matsuura ,  Yoshito Nakazawa ,  Tsuyoshi Kachi ,  Yuji Yatsuda

IPC分类号： H01L27/108

CPC分类号： H01L27/0629 ,  H01L21/26586 ,  H01L21/76897 ,  H01L29/0615 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8725

摘要： A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.

摘要翻译： 栅极沟槽13形成在半导体衬底10中。栅极沟槽13设置有形成在栅极绝缘膜14上的栅电极16.栅电极16的一部分从半导体衬底10突出，侧壁24为 形成在突出部分的侧壁部分上。 形成与相邻的栅电极16对准的主体沟槽25.在栅电极16的表面上并在主体沟槽25的表面之上形成硅化钴膜28.使用SAC技术形成插塞34。

公开(公告)号：US20050167746A1

公开(公告)日：2005-08-04

申请号：US11097295

申请日：2005-04-04

申请人： Yoshito Nakazawa ,  Yuji Yatsuda

发明人： Yoshito Nakazawa ,  Yuji Yatsuda

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/78 ,  H01L29/15

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

摘要： Heightening of breakdown voltage of a trench gate type power MISFET is actualized without increasing the number of manufacturing steps. In the manufacturing method of the semiconductor device according to the present invention, p− type semiconductor region and p− type field limiting rings are formed in a gate line area simultaneously in one impurity ion implantation step so as to bring them into contact with a groove having a gate extraction electrode formed therein. Upon formation, supposing that the width of the gate extraction electrode disposed outside the groove is CHSP, and the resistivity of the n− type single crystal silicon layer 1B is ρ (Ω·cm), the CHSP is set to satisfy the following equation: CHSP≦3.80+0.14892 .

摘要翻译： 实现沟槽栅型功率MISFET的击穿电压的升高而不增加制造步骤的数量。 在根据本发明的半导体器件的制造方法中，在一个栅极线区域中同时形成p +型半导体区域和p-O +型场限制环 杂质离子注入步骤使其与形成有栅极引出电极的沟槽接触。 在形成时，假设设置在沟槽外侧的栅极引出电极的宽度为CHSP，并且n +型单晶硅层1B的电阻率为rho（Ω·cm），则CHSP为 设定为满足以下等式：CHSP <= 3.80 + 0.148 92。

公开(公告)号：US20100327359A1

公开(公告)日：2010-12-30

申请号：US12873495

申请日：2010-09-01

申请人： Yoshito NAKAZAWA ,  Yuji Yatsuda

发明人： Yoshito NAKAZAWA ,  Yuji Yatsuda

IPC分类号： H01L27/06

CPC分类号： H01L29/7808 ,  H01L21/28008 ,  H01L21/28556 ,  H01L27/0255 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

摘要： In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n+-type semiconductor region of the protective diode are formed in the same step.

摘要翻译： 在具有具有虚拟栅电极的沟槽栅极结构的功率MISFET中，提供了用于改善功率MISFET的性能的技术，同时防止其中的栅极绝缘膜的静电击穿。 在相同的半导体衬底上形成具有具有虚拟栅电极的沟槽栅极结构和保护二极管的功率MISFET。 保护二极管设置在源电极和栅极互连之间。 在这种半导体器件的制造方法中，同时形成用于伪栅电极的多晶硅膜和用于保护二极管的多晶硅膜。 在同一步骤中形成功率MISFET的源极区域和保护二极管的n +型半导体区域。

公开(公告)号：US07847347B2

公开(公告)日：2010-12-07

申请号：US12724409

申请日：2010-03-15

申请人： Hitoshi Matsuura ,  Yoshito Nakazawa ,  Tsuyoshi Kachi ,  Yuji Yatsuda

发明人： Hitoshi Matsuura ,  Yoshito Nakazawa ,  Tsuyoshi Kachi ,  Yuji Yatsuda

IPC分类号： H01L27/108

CPC分类号： H01L27/0629 ,  H01L21/26586 ,  H01L21/76897 ,  H01L29/0615 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8725

摘要： A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.

公开(公告)号：US20090224315A1

公开(公告)日：2009-09-10

申请号：US12463962

申请日：2009-05-11

申请人： Hitoshi Matsuura ,  Yoshito Nakazawa ,  Tsuyoshi Kachi ,  Yuji Yatsuda

发明人： Hitoshi Matsuura ,  Yoshito Nakazawa ,  Tsuyoshi Kachi ,  Yuji Yatsuda

IPC分类号： H01L29/78

CPC分类号： H01L27/0629 ,  H01L21/26586 ,  H01L21/76897 ,  H01L29/0615 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8725

摘要： A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.

摘要翻译： 栅极沟槽13形成在半导体衬底10中。栅极沟槽13设置有形成在栅极绝缘膜14上的栅电极16.栅电极16的一部分从半导体衬底10突出，侧壁24为 形成在突出部分的侧壁部分上。 形成与相邻的栅电极16对准的主体沟槽25.在栅电极16的表面上并在主体沟槽25的表面之上形成硅化钴膜28.使用SAC技术形成插塞34。

公开(公告)号：US20080035990A1

公开(公告)日：2008-02-14

申请号：US11836574

申请日：2007-08-09

申请人： Hitoshi Matsuura ,  Yoshito Nakazawa ,  Tsuyoshi Kachi ,  Yuji Yatsuda

发明人： Hitoshi Matsuura ,  Yoshito Nakazawa ,  Tsuyoshi Kachi ,  Yuji Yatsuda

IPC分类号： H01L21/336 ,  H01L29/772

CPC分类号： H01L27/0629 ,  H01L21/26586 ,  H01L21/76897 ,  H01L29/0615 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8725

摘要： A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.

摘要翻译： 在半导体衬底10中形成栅沟槽13。 栅极沟槽13设置有形成在栅极绝缘膜14上的栅电极16。 栅电极16的一部分从半导体基板10突出，并且在突出部分的侧壁部分上形成侧壁24。 主体沟槽25形成为与相邻的栅电极16对准。 在栅电极16的表面上并在体沟槽25的表面上形成钴硅化物膜28。 使用SAC技术形成插头34。

公开(公告)号：US07211862B2

公开(公告)日：2007-05-01

申请号：US11249335

申请日：2005-10-14

申请人： Yoshito Nakazawa ,  Yuji Yatsuda

发明人： Yoshito Nakazawa ,  Yuji Yatsuda

IPC分类号： H01L29/94

CPC分类号： H01L29/7813 ,  H01L21/2652 ,  H01L21/26586 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/66727

摘要： A semiconductor device wherein an avalanche withstand of power MISFET is improved without enlarging cell pitch. In the semiconductor device, impurity ions having a p-type conduction, e.g. B ions, are introduced from a bottom of a contact hole to form a p-type semiconductive region that is provided below a p+-type semiconductive region and in contact with the p+-type semiconductive region and an n−-type single crystal silicon layer and that has an impurity concentration lower than the p+-type semiconductive region. An n-type semiconductive region is formed in the n−-type single crystal silicon layer provided below the p-type semiconductive region as being in contact with the p-type semiconductive region and has an impurity concentration lower than the n−-type single crystal silicon layer.

摘要翻译： 一种半导体器件，其中在不增加电池间距的情况下改善功率MISFET的雪崩承受能力。 在半导体器件中，具有p型导电的杂质离子，例如， B离子从接触孔的底部引入以形成p型半导体区域，其设置在p + +型半导体区域下方并与p + >型半导体区域和n + O型单晶硅层，并且其杂质浓度低于p + + H +型半导体区域。 在p型半导体区域下方设置的n型半导体区域形成n型半导体区域，与p型半导体区域接触，杂质浓度越低 比n + - 型单晶硅层。

公开(公告)号：US06885061B2

公开(公告)日：2005-04-26

申请号：US10827295

申请日：2004-04-20

申请人： Yoshito Nakazawa ,  Yuji Yatsuda

发明人： Yoshito Nakazawa ,  Yuji Yatsuda

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

摘要： Heightening of breakdown voltage of a trench gate type power MISFET is actualized without increasing the number of manufacturing steps. In the manufacturing method of the semiconductor device according to the present invention, p− type semiconductor region and p− type field limiting rings are formed in a gate line area simultaneously in one impurity ion implantation step so as to bring them into contact with a groove having a gate extraction electrode formed therein. Upon formation, supposing that the width of the gate extraction electrode disposed outside the groove is CHSP, and the resistivity of the n− type single crystal silicon layer 1B is ρ (Ω·cm), the CHSP is set to satisfy the following equation: CHSP≦3.80+0.148 ρ.

摘要翻译： 实现沟槽栅型功率MISFET的击穿电压的升高而不增加制造步骤的数量。 在根据本发明的半导体器件的制造方法中，在一个栅极线区域中同时形成p +型半导体区域和p-O +型场限制环 杂质离子注入步骤使其与形成有栅极引出电极的沟槽接触。 在形成时，假设设置在沟槽外侧的栅极引出电极的宽度为CHSP，并且n +型单晶硅层1B的电阻率为rho（Ω·cm），则CHSP 设定为满足以下等式：CHSP <= 3.80 + 0.148 rho。

公开(公告)号：US07834407B2

公开(公告)日：2010-11-16

申请号：US12471680

申请日：2009-05-26

申请人： Yoshito Nakazawa ,  Yuji Yatsuda

发明人： Yoshito Nakazawa ,  Yuji Yatsuda

IPC分类号： H01L27/088

CPC分类号： H01L29/7808 ,  H01L21/28008 ,  H01L21/28556 ,  H01L27/0255 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

摘要： In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n+-type semiconductor region of the protective diode are formed in the same step.

摘要翻译： 在具有具有虚拟栅电极的沟槽栅极结构的功率MISFET中，提供了用于改善功率MISFET的性能的技术，同时防止其中的栅极绝缘膜的静电击穿。 在相同的半导体衬底上形成具有具有虚拟栅电极的沟槽栅极结构和保护二极管的功率MISFET。 保护二极管设置在源电极和栅极互连之间。 在这种半导体器件的制造方法中，同时形成用于伪栅电极的多晶硅膜和用于保护二极管的多晶硅膜。 在同一步骤中形成功率MISFET的源极区域和保护二极管的n +型半导体区域。