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    Edge devices layout for improved performance
    3.
    发明授权
    Edge devices layout for improved performance 有权
    边缘设备布局，以提高性能

    公开(公告)号：US08610236B2

    公开(公告)日：2013-12-17

    申请号：US12851702

    申请日：2010-08-06

    申请人： Yen-Huei Chen ,  Jung-Hsuan Chen ,  Shao-Yu Chou ,  Hung-Jen Liao ,  Li-Chun Tien

    发明人： Yen-Huei Chen ,  Jung-Hsuan Chen ,  Shao-Yu Chou ,  Hung-Jen Liao ,  Li-Chun Tien

    IPC分类号： H01L27/08

    CPC分类号： H01L21/28008 ,  H01L21/28123 ,  H01L21/823425 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/66628 ,  H01L29/7848

    摘要： A word line driver includes an active area having a length that extends in a first direction over a semiconductor substrate. A plurality of fingers formed over an upper surface of the active area. Each of the plurality of fingers has a length that extends in a second direction and forms a MOS transistor with a portion of the active area. A first dummy structure is disposed between an outer one of the plurality of fingers and an edge of the semiconductor substrate. The first dummy structure includes a portion that is at least partially disposed over a portion of the active area.

    摘要翻译： 字线驱动器包括具有沿半导体衬底的第一方向延伸的长度的有源区。 多个指状物形成在有源区域的上表面上。 多个指状物中的每一个具有在第二方向上延伸的长度，并且形成具有有效区域的一部分的MOS晶体管。 第一虚设结构设置在多个指状物的外部之一和半导体衬底的边缘之间。 第一虚拟结构包括至少部分地设置在有效区域的一部分上的部分。

    LAYOUT SCHEME AND METHOD FOR FORMING DEVICE CELLS IN SEMICONDUCTOR DEVICES
    4.
    发明申请
    LAYOUT SCHEME AND METHOD FOR FORMING DEVICE CELLS IN SEMICONDUCTOR DEVICES 有权
    用于在半导体器件中形成器件电池的布局方案和方法

    公开(公告)号：US20120256235A1

    公开(公告)日：2012-10-11

    申请号：US13082497

    申请日：2011-04-08

    申请人： Hsien-Yu Pan ,  Jung-Hsuan Chen ,  Shao-Yu Chou ,  Yen-Huei Chen ,  Hung-Jen Liao

    发明人： Hsien-Yu Pan ,  Jung-Hsuan Chen ,  Shao-Yu Chou ,  Yen-Huei Chen ,  Hung-Jen Liao

    IPC分类号： H01L23/52 ,  H01L21/768

    CPC分类号： H01L27/1116 ,  H01L21/768 ,  H01L27/0207 ,  H01L27/11 ,  H01L2027/11887

    摘要： A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.

    摘要翻译： 用于形成字线解码器装置和具有字线解码器单元的其它装置的方法和布局提供了使用非DPL光刻操作形成金属互连层，并且使用下部或中间金属层或下部导电材料提供了用于缝合的远端布置的晶体管。 晶体管可以设置在纵向布置的字线解码器或其他单元中或其附近，并且使用金属或导电材料的导电耦合降低晶体管之间的栅极电阻并避免RC信号延迟。

    Semiconductor device for word line driver with efficient routing of conductor for decreased gate resistance
    6.
    发明授权
    Semiconductor device for word line driver with efficient routing of conductor for decreased gate resistance 有权
    用于字线驱动器的半导体器件，具有用于降低栅极电阻的导体的有效布线

    公开(公告)号：US08692333B2

    公开(公告)日：2014-04-08

    申请号：US12855004

    申请日：2010-08-12

    申请人： Yen-Huei Chen ,  You-Cheng Xiao ,  Jung-Hsuan Chen ,  Shao-Yu Chou

    发明人： Yen-Huei Chen ,  You-Cheng Xiao ,  Jung-Hsuan Chen ,  Shao-Yu Chou

    IPC分类号： H01L29/76

    CPC分类号： H01L21/82385 ,  G11C8/08 ,  G11C8/14

    摘要： A semiconductor device comprises first, second, and third. The first conductor is a gate conductor formed above an oxide region over a substrate and having a contact. The second conductor is coupled to the contact and extends across a width of the oxide region. The second conductor has a lower resistance than the gate conductor. The third conductor is a word line conductor. The second conductor is routed to not intersect the word line conductor.

    摘要翻译： 半导体器件包括第一，第二和第三。 第一导体是形成在衬底上方并具有接触的氧化物区域上方的栅极导体。 第二导体耦合到触点并延伸穿过氧化物区域的宽度。 第二导体的电阻低于栅极导体。 第三导体是字线导体。 第二个导体被路由到不与字线导体相交。

    Layouts of POLY Cut Openings Overlapping Active Regions
    7.
    发明申请
    Layouts of POLY Cut Openings Overlapping Active Regions 有权
    POLY切割开关重叠活动区域的布局

    公开(公告)号：US20120258592A1

    公开(公告)日：2012-10-11

    申请号：US13081115

    申请日：2011-04-06

    申请人： Jung-Hsuan Chen ,  Yen-Huei Chen ,  Li-Chun Tien ,  Hung-Jen Liao

    发明人： Jung-Hsuan Chen ,  Yen-Huei Chen ,  Li-Chun Tien ,  Hung-Jen Liao

    IPC分类号： H01L21/28

    CPC分类号： H01L21/32139 ,  H01L21/76816

    摘要： A method of forming integrated circuits includes forming a mask layer over a gate electrode line, wherein the gate electrode line is over a well region of a semiconductor substrate; forming an opening in the mask layer, wherein a portion of the gate electrode line and a well pickup region of the well region are exposed through the opening; and removing the portion of the gate electrode line through the opening.

    摘要翻译： 形成集成电路的方法包括在栅电极线上形成掩模层，其中栅电极线在半导体衬底的阱区之上; 在所述掩模层中形成开口，其中所述栅电极线的一部分和所述阱区的阱拾取区域通过所述开口露出; 并且通过所述开口去除所述栅电极线的所述部分。

    Layouts of POLY cut openings overlapping active regions
    8.
    发明授权
    Layouts of POLY cut openings overlapping active regions 有权
    POLY切割开口与活跃区域重叠的布局

    公开(公告)号：US08455354B2

    公开(公告)日：2013-06-04

    申请号：US13081115

    申请日：2011-04-06

    申请人： Jung-Hsuan Chen ,  Yen-Huei Chen ,  Li-Chun Tien ,  Hung-Jen Liao

    发明人： Jung-Hsuan Chen ,  Yen-Huei Chen ,  Li-Chun Tien ,  Hung-Jen Liao

    IPC分类号： H01L21/28

    CPC分类号： H01L21/32139 ,  H01L21/76816

    摘要： A method of forming integrated circuits includes forming a mask layer over a gate electrode line, wherein the gate electrode line is over a well region of a semiconductor substrate; forming an opening in the mask layer, wherein a portion of the gate electrode line and a well pickup region of the well region are exposed through the opening; and removing the portion of the gate electrode line through the opening.

    摘要翻译： 形成集成电路的方法包括在栅电极线上形成掩模层，其中栅电极线在半导体衬底的阱区之上; 在所述掩模层中形成开口，其中所述栅电极线的一部分和所述阱区的阱拾取区域通过所述开口露出; 并且通过所述开口去除所述栅电极线的所述部分。

    SRAM bit cell
    9.
    发明授权
    SRAM bit cell 有权
    SRAM位单元

    公开(公告)号：US08363454B2

    公开(公告)日：2013-01-29

    申请号：US13015773

    申请日：2011-01-28

    申请人： Ping Wang ,  Hung-Jen Liao ,  Yen-Huei Chen ,  Jihi-Yu Lin ,  Shao-Yu Chou

    发明人： Ping Wang ,  Hung-Jen Liao ,  Yen-Huei Chen ,  Jihi-Yu Lin ,  Shao-Yu Chou

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412

    摘要： A semiconductor memory bit cell includes an inverter latch including a pair of cross-coupled inverters. A first transistor has a gate coupled to a first control line and a source coupled to the inverter latch, and a second transistor has a gate coupled to a second control line and a drain coupled to the drain of the first transistor at a first node. A third transistor has a source coupled to the first node and a gate coupled to a word line, and a fourth transistor has a gate coupled to a source of the second transistor and to the inverter latch. A fifth transistor has a gate coupled to the word line and a drain coupled to a read bit line.

    摘要翻译： 半导体存储器位单元包括具有一对交叉耦合的反相器的反相器锁存器。 第一晶体管具有耦合到第一控制线的栅极和耦合到反相器锁存器的源极，并且第二晶体管具有耦合到第二控制线的栅极和在第一节点耦合到第一晶体管的漏极的漏极。 第三晶体管具有耦合到第一节点的源极和耦合到字线的栅极，并且第四晶体管具有耦合到第二晶体管的源极和反相器锁存器的栅极。 第五晶体管具有耦合到字线的栅极和耦合到读位线的漏极。

    Distributed VDC for SRAM Memory
    10.
    发明申请
    Distributed VDC for SRAM Memory 有权
    分布式VDC用于SRAM存储器

    公开(公告)号：US20100157692A1

    公开(公告)日：2010-06-24

    申请号：US12338732

    申请日：2008-12-18

    申请人： Li-Wen Wang ,  Yen-Huei Chen ,  Chen-Lin Yang ,  Hsien-Yu Pan ,  Shao-Yu Chou ,  Hung-Jen Liao

    发明人： Li-Wen Wang ,  Yen-Huei Chen ,  Chen-Lin Yang ,  Hsien-Yu Pan ,  Shao-Yu Chou ,  Hung-Jen Liao

    IPC分类号： G11C7/00 ,  G11C5/14

    CPC分类号： G11C11/413 ,  G11C5/04 ,  G11C5/147

    摘要： An integrated circuit structure includes a memory. The memory includes a first memory macro and a second memory macro identical to the first memory macro. A first power block is connected to the first memory macro and is configured to provide a regulated voltage to the first memory macro. The first power block has a first input and a first output. A second power block substantially identical to the first power block is connected to the second memory macro and is configured to provide the regulated voltage to the second memory macro. The second power block has a second input and a second output. The first input and the second input are interconnected. The first output and the second output are interconnected.

    摘要翻译： 集成电路结构包括存储器。 存储器包括与第一存储器宏相同的第一存储器宏和第二存储器宏。 第一功率块连接到第一存储器宏，并被配置为向第一存储器宏提供调节电压。 第一功率块具有第一输入和第一输出。 基本上与第一功率块相同的第二功率块连接到第二存储器宏，并且被配置为向第二存储器宏提供调节电压。 第二功率块具有第二输入和第二输出。 第一输入和第二输入互连。 第一个输出和第二个输出相互连接。