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    Edge devices layout for improved performance
    3.
    发明授权
    Edge devices layout for improved performance 有权
    边缘设备布局，以提高性能

    公开(公告)号：US08610236B2

    公开(公告)日：2013-12-17

    申请号：US12851702

    申请日：2010-08-06

    申请人： Yen-Huei Chen ,  Jung-Hsuan Chen ,  Shao-Yu Chou ,  Hung-Jen Liao ,  Li-Chun Tien

    发明人： Yen-Huei Chen ,  Jung-Hsuan Chen ,  Shao-Yu Chou ,  Hung-Jen Liao ,  Li-Chun Tien

    IPC分类号： H01L27/08

    CPC分类号： H01L21/28008 ,  H01L21/28123 ,  H01L21/823425 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/66628 ,  H01L29/7848

    摘要： A word line driver includes an active area having a length that extends in a first direction over a semiconductor substrate. A plurality of fingers formed over an upper surface of the active area. Each of the plurality of fingers has a length that extends in a second direction and forms a MOS transistor with a portion of the active area. A first dummy structure is disposed between an outer one of the plurality of fingers and an edge of the semiconductor substrate. The first dummy structure includes a portion that is at least partially disposed over a portion of the active area.

    摘要翻译： 字线驱动器包括具有沿半导体衬底的第一方向延伸的长度的有源区。 多个指状物形成在有源区域的上表面上。 多个指状物中的每一个具有在第二方向上延伸的长度，并且形成具有有效区域的一部分的MOS晶体管。 第一虚设结构设置在多个指状物的外部之一和半导体衬底的边缘之间。 第一虚拟结构包括至少部分地设置在有效区域的一部分上的部分。

    LAYOUT SCHEME AND METHOD FOR FORMING DEVICE CELLS IN SEMICONDUCTOR DEVICES
    4.
    发明申请
    LAYOUT SCHEME AND METHOD FOR FORMING DEVICE CELLS IN SEMICONDUCTOR DEVICES 有权
    用于在半导体器件中形成器件电池的布局方案和方法

    公开(公告)号：US20120256235A1

    公开(公告)日：2012-10-11

    申请号：US13082497

    申请日：2011-04-08

    申请人： Hsien-Yu Pan ,  Jung-Hsuan Chen ,  Shao-Yu Chou ,  Yen-Huei Chen ,  Hung-Jen Liao

    发明人： Hsien-Yu Pan ,  Jung-Hsuan Chen ,  Shao-Yu Chou ,  Yen-Huei Chen ,  Hung-Jen Liao

    IPC分类号： H01L23/52 ,  H01L21/768

    CPC分类号： H01L27/1116 ,  H01L21/768 ,  H01L27/0207 ,  H01L27/11 ,  H01L2027/11887

    摘要： A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.

    摘要翻译： 用于形成字线解码器装置和具有字线解码器单元的其它装置的方法和布局提供了使用非DPL光刻操作形成金属互连层，并且使用下部或中间金属层或下部导电材料提供了用于缝合的远端布置的晶体管。 晶体管可以设置在纵向布置的字线解码器或其他单元中或其附近，并且使用金属或导电材料的导电耦合降低晶体管之间的栅极电阻并避免RC信号延迟。

    Semiconductor device for word line driver with efficient routing of conductor for decreased gate resistance
    5.
    发明授权
    Semiconductor device for word line driver with efficient routing of conductor for decreased gate resistance 有权
    用于字线驱动器的半导体器件，具有用于降低栅极电阻的导体的有效布线

    公开(公告)号：US08692333B2

    公开(公告)日：2014-04-08

    申请号：US12855004

    申请日：2010-08-12

    申请人： Yen-Huei Chen ,  You-Cheng Xiao ,  Jung-Hsuan Chen ,  Shao-Yu Chou

    发明人： Yen-Huei Chen ,  You-Cheng Xiao ,  Jung-Hsuan Chen ,  Shao-Yu Chou

    IPC分类号： H01L29/76

    CPC分类号： H01L21/82385 ,  G11C8/08 ,  G11C8/14

    摘要： A semiconductor device comprises first, second, and third. The first conductor is a gate conductor formed above an oxide region over a substrate and having a contact. The second conductor is coupled to the contact and extends across a width of the oxide region. The second conductor has a lower resistance than the gate conductor. The third conductor is a word line conductor. The second conductor is routed to not intersect the word line conductor.

    摘要翻译： 半导体器件包括第一，第二和第三。 第一导体是形成在衬底上方并具有接触的氧化物区域上方的栅极导体。 第二导体耦合到触点并延伸穿过氧化物区域的宽度。 第二导体的电阻低于栅极导体。 第三导体是字线导体。 第二个导体被路由到不与字线导体相交。

    Layouts of POLY Cut Openings Overlapping Active Regions
    7.
    发明申请
    Layouts of POLY Cut Openings Overlapping Active Regions 有权
    POLY切割开关重叠活动区域的布局

    公开(公告)号：US20120258592A1

    公开(公告)日：2012-10-11

    申请号：US13081115

    申请日：2011-04-06

    申请人： Jung-Hsuan Chen ,  Yen-Huei Chen ,  Li-Chun Tien ,  Hung-Jen Liao

    发明人： Jung-Hsuan Chen ,  Yen-Huei Chen ,  Li-Chun Tien ,  Hung-Jen Liao

    IPC分类号： H01L21/28

    CPC分类号： H01L21/32139 ,  H01L21/76816

    摘要： A method of forming integrated circuits includes forming a mask layer over a gate electrode line, wherein the gate electrode line is over a well region of a semiconductor substrate; forming an opening in the mask layer, wherein a portion of the gate electrode line and a well pickup region of the well region are exposed through the opening; and removing the portion of the gate electrode line through the opening.

    摘要翻译： 形成集成电路的方法包括在栅电极线上形成掩模层，其中栅电极线在半导体衬底的阱区之上; 在所述掩模层中形成开口，其中所述栅电极线的一部分和所述阱区的阱拾取区域通过所述开口露出; 并且通过所述开口去除所述栅电极线的所述部分。

    Layouts of POLY cut openings overlapping active regions
    8.
    发明授权
    Layouts of POLY cut openings overlapping active regions 有权
    POLY切割开口与活跃区域重叠的布局

    公开(公告)号：US08455354B2

    公开(公告)日：2013-06-04

    申请号：US13081115

    申请日：2011-04-06

    申请人： Jung-Hsuan Chen ,  Yen-Huei Chen ,  Li-Chun Tien ,  Hung-Jen Liao

    发明人： Jung-Hsuan Chen ,  Yen-Huei Chen ,  Li-Chun Tien ,  Hung-Jen Liao

    IPC分类号： H01L21/28

    CPC分类号： H01L21/32139 ,  H01L21/76816

    摘要： A method of forming integrated circuits includes forming a mask layer over a gate electrode line, wherein the gate electrode line is over a well region of a semiconductor substrate; forming an opening in the mask layer, wherein a portion of the gate electrode line and a well pickup region of the well region are exposed through the opening; and removing the portion of the gate electrode line through the opening.

    摘要翻译： 形成集成电路的方法包括在栅电极线上形成掩模层，其中栅电极线在半导体衬底的阱区之上; 在所述掩模层中形成开口，其中所述栅电极线的一部分和所述阱区的阱拾取区域通过所述开口露出; 并且通过所述开口去除所述栅电极线的所述部分。

    Memory edge cell
    9.
    发明授权
    Memory edge cell 有权
    内存边缘单元格

    公开(公告)号：US08482990B2

    公开(公告)日：2013-07-09

    申请号：US13025872

    申请日：2011-02-11

    申请人： Hong-Chen Cheng ,  Ming-Yi Lee ,  Kuo-Hua Pan ,  Jung-Hsuan Chen ,  Li-Chun Tien ,  Cheng Hung Lee ,  Hung-Jen Liao

    发明人： Hong-Chen Cheng ,  Ming-Yi Lee ,  Kuo-Hua Pan ,  Jung-Hsuan Chen ,  Li-Chun Tien ,  Cheng Hung Lee ,  Hung-Jen Liao

    IPC分类号： G11C7/10

    CPC分类号： G11C5/06 ,  G11C5/147 ,  G11C5/148 ,  G11C11/417

    摘要： A circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The PMOS transistors and the NMOS transistors are configured to provide a first voltage reference node having a first reference voltage and a second voltage reference node having a second reference voltage. The first reference voltage and the second reference voltage serve as a first reference voltage and a second reference voltage for a memory cell, respectively.

    摘要翻译： 电路包括第一PMOS晶体管，第二PMOS晶体管，第一NMOS晶体管，第二NMOS晶体管，第三NMOS晶体管和第四NMOS晶体管。 PMOS晶体管和NMOS晶体管被配置为提供具有第一参考电压的第一电压参考节点和具有第二参考电压的第二参考电压节点。 第一参考电压和第二参考电压分别用作存储器单元的第一参考电压和第二参考电压。

    Method and apparatus for word line decoder layout
    10.
    发明授权
    Method and apparatus for word line decoder layout 有权
    字线解码器布局的方法和装置

    公开(公告)号：US08837250B2

    公开(公告)日：2014-09-16

    申请号：US12839490

    申请日：2010-07-20

    申请人： You-Cheng Xiao ,  Hong-Chen Cheng ,  Chung-Ji Lu ,  Cheng Hung Lee ,  Jung-Hsuan Chen ,  Li-Chun Tien

    发明人： You-Cheng Xiao ,  Hong-Chen Cheng ,  Chung-Ji Lu ,  Cheng Hung Lee ,  Jung-Hsuan Chen ,  Li-Chun Tien

    IPC分类号： G11C8/10

    CPC分类号： G11C8/10 ,  G11C11/413

    摘要： A word line decoder comprises a plurality of driver circuits, a plurality of word lines provided at respective outputs of the driver circuits, and a plurality of primary input lines coupled to the driver circuits and oriented in a first direction. The word line decoder also comprises a plurality of secondary input lines coupled to the driver circuits and oriented in the first direction. The word line decoder also comprises a local decode line coupled to each of the primary input lines. The word line decoder also comprises a decode line coupled to the local decode line and oriented in the first direction. A cluster decode line is coupled to the decode line. The word line decoder is configured to select at least one of the word lines based on signals provided by the cluster decode line and the secondary input lines.

    摘要翻译： 字线解码器包括多个驱动器电路，设置在驱动器电路的各个输出处的多个字线以及耦合到驱动器电路并沿第一方向取向的多个主输入线。 字线解码器还包括耦合到驱动器电路并沿第一方向定向的多个次级输入线。 字线解码器还包括耦合到每个主输入线的本地解码线。 字线解码器还包括耦合到本地解码线并沿第一方向定向的解码线。 集群解码线耦合到解码线。 字线解码器被配置为基于由群集解码线和辅助输入线提供的信号来选择至少一个字线。