公开(公告)号：US08648420B2

公开(公告)日：2014-02-11

申请号：US12849737

申请日：2010-08-03

申请人： Young-Chul Kim ,  Il-Kwon Chang ,  Ji-Ho Lew ,  Kyoung-Sik Kim ,  So-Youn Kim

发明人： Young-Chul Kim ,  Il-Kwon Chang ,  Ji-Ho Lew ,  Kyoung-Sik Kim ,  So-Youn Kim

IPC分类号： H01L23/62

CPC分类号： H01L27/0266

摘要： A semiconductor device includes an input/output pad, and a data transfer unit configured to form a parasitic diode between the input/output pad and a power supply terminal thereof to discharge an introduced electrostatic discharge (ESD), and form a data transfer path between the input/output pad and an internal circuit in response to a control signal.

摘要翻译： 半导体器件包括输入/​​输出焊盘和数据传输单元，其被配置为在输入/输出焊盘和其电源端之间形成寄生二极管，以放电引入的静电放电（ESD），并且形成数据传输路径， 输入/输出焊盘和响应于控制信号的内部电路。

公开(公告)号：US20060158420A1

公开(公告)日：2006-07-20

申请号：US11208498

申请日：2005-08-22

申请人： Il-Kwon Chang ,  Yong-Weon Jeon

发明人： Il-Kwon Chang ,  Yong-Weon Jeon

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G2310/027 ,  G09G2330/021 ,  G09G2330/06

摘要： For generating source line voltages in a display device, gray scale data is received at a source driver for a first sub-pixel of a pixel. The source driver generates a first source line voltage for the first sub-pixel and a second source line voltage for a second sub-pixel from the gray scale data of the first sub-pixel. Thus, data transfer rate and/or data buses are minimized for in turn minimizing power consumption and EMI (electromagnetic interference).

公开(公告)号：US20080309538A1

公开(公告)日：2008-12-18

申请号：US11556729

申请日：2006-11-06

申请人： Il-Kwon Chang ,  Yong-Weon Jeon ,  Ji-Woon Jung

发明人： Il-Kwon Chang ,  Yong-Weon Jeon ,  Ji-Woon Jung

IPC分类号： H03M1/68

CPC分类号： H03M1/687 ,  H03M1/667 ,  H03M1/682 ,  H03M1/765

摘要： A digital/analog converting driver and a digital/analog converting method, in which the digital/analog converting driver converts digital data having M+N (M and N are integers) bits into an analog voltage and includes a first converting unit, a second converting unit, and an analog voltage outputting unit. The first converting unit converts successive M bits of the digital data into a first voltage. The second converting unit converts successive N bits of the digital data into a second voltage. The analog voltage outputting unit adds the first voltage and the second voltage and outputs the added voltage as the analog voltage. The output range of the first voltage is different from that of the second voltage.

摘要翻译： 数字/模拟转换驱动器和数字/模拟转换方法，其中数字/模拟转换驱动器将具有M + N（M和N为整数）位的数字数据转换成模拟电压，并且包括第一转换单元，第二转换单元 转换单元和模拟电压输出单元。 第一转换单元将数字数据的连续M位转换为第一电压。 第二转换单元将数字数据的连续N位转换为第二电压。 模拟电压输出单元将第一电压和第二电压相加，并输出相加的电压作为模拟电压。 第一电压的输出范围不同于第二电压的输出范围。

公开(公告)号：US07612788B2

公开(公告)日：2009-11-03

申请号：US11208498

申请日：2005-08-22

申请人： Il-Kwon Chang ,  Yong-Weon Jeon

发明人： Il-Kwon Chang ,  Yong-Weon Jeon

IPC分类号： G09G5/10

CPC分类号： G09G3/3688 ,  G09G2310/027 ,  G09G2330/021 ,  G09G2330/06

摘要： For generating source line voltages in a display device, gray scale data is received at a source driver for a first sub-pixel of a pixel. The source driver generates a first source line voltage for the first sub-pixel and a second source line voltage for a second sub-pixel from the gray scale data of the first sub-pixel. Thus, data transfer rate and/or data buses are minimized for in turn minimizing power consumption and EMI (electromagnetic interference).

摘要翻译： 为了在显示装置中产生源极线电压，在像素的第一子像素的源极驱动器处接收灰度数据。 源极驱动器从第一子像素的灰度数据产生用于第一子像素的第一源极线电压和用于第二子像素的第二源极线电压。 因此，数据传输速率和/或数据总线被最小化，从而最小化功耗和EMI（电磁干扰）。

公开(公告)号：US07609191B2

公开(公告)日：2009-10-27

申请号：US11556729

申请日：2006-11-06

申请人： Il-Kwon Chang ,  Yong-Weon Jeon ,  Ji-Woon Jung

发明人： Il-Kwon Chang ,  Yong-Weon Jeon ,  Ji-Woon Jung

IPC分类号： H03M1/68

CPC分类号： H03M1/687 ,  H03M1/667 ,  H03M1/682 ,  H03M1/765

摘要： A digital/analog converting driver and a digital/analog converting method, in which the digital/analog converting driver converts digital data having M+N (M and N are integers) bits into an analog voltage and includes a first converting unit, a second converting unit, and an analog voltage outputting unit. The first converting unit converts successive M bits of the digital data into a first voltage. The second converting unit converts successive N bits of the digital data into a second voltage. The analog voltage outputting unit adds the first voltage and the second voltage and outputs the added voltage as the analog voltage. The output range of the first voltage is different from that of the second voltage.

摘要翻译： 数字/模拟转换驱动器和数字/模拟转换方法，其中数字/模拟转换驱动器将具有M + N（M和N为整数）位的数字数据转换成模拟电压，并且包括第一转换单元，第二转换单元 转换单元和模拟电压输出单元。 第一转换单元将数字数据的连续M位转换为第一电压。 第二转换单元将数字数据的连续N位转换为第二电压。 模拟电压输出单元将第一电压和第二电压相加，并输出相加的电压作为模拟电压。 第一电压的输出范围不同于第二电压的输出范围。

公开(公告)号：US07310005B2

公开(公告)日：2007-12-18

申请号：US11302438

申请日：2005-12-14

申请人： Il-Kwon Chang ,  Yong-Weon Jeon ,  Kyung-Wol Kim

发明人： Il-Kwon Chang ,  Yong-Weon Jeon ,  Kyung-Wol Kim

IPC分类号： H03R19/0175

CPC分类号： G11C5/063 ,  H03M7/04 ,  H03M7/06 ,  H04L25/0282 ,  H04L25/4917

摘要： Provided are a receiver and a transceiver for multi-level current-mode signaling, which together may reduce the number of bus lines and increase a data bandwidth. A transmitter transmits one reference current and a multi-level data current. On the basis of the reference current signal received from the transmitter, a receiver generates plural internal reference currents for determining the multi-level data current received from the transmitter, and converting the received multi-level data current into a data voltage having the desired level corresponding to the data that was transmitted.

摘要翻译： 提供了用于多电平电流模式信令的接收机和收发器，它们可以一起减少总线数量并增加数据带宽。 发射机发送一个参考电流和多电平数据电流。 基于从发射机接收的参考电流信号，接收器产生多个内部参考电流，用于确定从发射机接收的多电平数据电流，并将接收到的多电平数据电流转换成具有期望电平的数据电压 对应于传输的数据。

公开(公告)号：US07279985B2

公开(公告)日：2007-10-09

申请号：US11053158

申请日：2005-02-07

申请人： Il-Kwon Chang ,  Yong-Weon Jeon

发明人： Il-Kwon Chang ,  Yong-Weon Jeon

IPC分类号： H03F1/22

CPC分类号： H03F1/223

摘要： A regulated cascode amplifier includes a main cascode amplifier and a feed-back amplifier. The main cascode amplifier has an input transistor coupled in a stack with an output transistor at an input control node. The feed-back amplifier including a plurality of transistors with gates of the transistors being coupled together to the input control node and with drains of the transistors being coupled together at a gate of the output transistor. The transistors of the feed-back amplifier are biased from connections to the main cascode amplifier for smaller chip area.

摘要翻译： 调节级联放大器包括主级联放大器和反馈放大器。 主级联放大器具有与输入控制节点处的输出晶体管堆叠的输入晶体管。 所述反馈放大器包括多个晶体管，所述晶体管的晶体管的栅极被耦合到输入控制节点，并且晶体管的漏极在输出晶体管的栅极耦合在一起。 反馈放大器的晶体管从连接到主级联放大器偏置较小的芯片面积。

公开(公告)号：US20070194964A1

公开(公告)日：2007-08-23

申请号：US11557694

申请日：2006-11-08

申请人： Il-Kwon Chang ,  Min-Gwang Kang

发明人： Il-Kwon Chang ,  Min-Gwang Kang

IPC分类号： H03M1/66

CPC分类号： H03M1/662 ,  H03M1/667 ,  H03M1/687

摘要： A digital-to-analog converter using capacitors and an operational amplifier, which can be highly integrated due to its small area and which can rapidly perform a stable converting operation. The digital-to-analog converter includes a data input unit, a first conversion unit, a second conversion unit, and a signal output unit. When digital data is input to the data input unit, the data input unit is connected to the first conversion unit or the second conversion unit. The first conversion unit charges a first charging capacitor with a voltage corresponding to the input digital data and distributes the charged charges to a first distribution capacitor. The second conversion unit charges a second charging capacitor with the voltage corresponding to the input digital data and distributes the charged charges to a second distribution capacitor. The signal output unit outputs an analog data signal corresponding to the voltage across the first distribution capacitor or the voltage across the second distribution capacitor in response to a select control signal.

摘要翻译： 使用电容器和运算放大器的数/模转换器，由于其面积小，可以高度集成，可以快速执行稳定的转换操作。 数模转换器包括数据输入单元，第一转换单元，第二转换单元和信号输出单元。 当数字数据被输入到数据输入单元时，数据输入单元连接到第一转换单元或第二转换单元。 第一转换单元用对应于输入数字数据的电压对第一充电电容器充电，并将充电电荷分配给第一分配电容器。 第二转换单元对与输入数字数据相对应的电压对第二充电电容器充电，并将充电电荷分配给第二分配电容器。 信号输出单元响应于选择控制信号输出对应于第一分配电容器两端的电压的模拟数据信号或第二分配电容器两端的电压。

公开(公告)号：US07259742B2

公开(公告)日：2007-08-21

申请号：US11302230

申请日：2005-12-14

申请人： Il-Kwon Chang ,  Yong-Weon Jeon

发明人： Il-Kwon Chang ,  Yong-Weon Jeon

IPC分类号： G09G3/36

CPC分类号： G09G3/20 ,  G09G3/3614 ,  G09G3/3685 ,  G09G2310/027 ,  G09G2310/0275 ,  G09G2310/08

摘要： A source driving circuit for a display device may include a first latch configured to store first video data corresponding to a first horizontal line and a second latch configured to store second video data corresponding to a second horizontal line following the first horizontal line. The first and second latches may alternately store video data of different horizontal lines. The source driving circuit may further include a digital-to-analog converter (DAC) configured to convert the stored first and second video data into analog signals, a first sample-and-hold circuit configured to sample and store an output signal of the DAC, a second sample-and-hold circuit configured to sample and store an output signal of the first sample-and-hold circuit, and an output switch configured to provide an output signal of the second sample-and-hold circuits to the display panel.

摘要翻译： 用于显示装置的源极驱动电路可以包括配置为存储对应于第一水平线的第一视频数据的第一锁存器和被配置为存储对应于第一水平线之后的第二水平线的第二视频数据的第二锁存器。 第一和第二锁存器可以交替地存储不同水平线的视频数据。 源极驱动电路还可以包括被配置为将所存储的第一和第二视频数据转换为模拟信号的数模转换器（DAC），第一采样保持电路被配置为对DAC的输出信号进行采样和存储 配置为采样并存储第一采样保持电路的输出信号的第二采样保持电路，以及配置成将第二采样保持电路的输出信号提供给显示面板的输出开关 。

公开(公告)号：US07436214B2

公开(公告)日：2008-10-14

申请号：US11223609

申请日：2005-09-09

申请人： Il-Kwon Chang ,  Yong-Weon Jeon

发明人： Il-Kwon Chang ,  Yong-Weon Jeon

IPC分类号： H03K19/0175

CPC分类号： H04L25/0294

摘要： A pseudo differential current mode receiver includes a regulated cascode buffer for buffering a received data current to generate a buffered data current with cascode-reduced input impedance and cascode-increased output impedance. In addition, a signal converter generates an output signal indicating a difference between the buffered data current and a reference current. The reference current may also be received and buffered by a regulated cascode buffer with cascode-reduced input impedance and cascode-increased output impedance.

摘要翻译： 伪差分电流模式接收器包括调节共源共栅缓冲器，用于缓冲接收到的数据电流以产生具有共源共栅降低的输入阻抗和共源共栅增加输出阻抗的缓冲数据电流。 此外，信号转换器产生指示缓冲的数据电流和参考电流之间的差的输出信号。 参考电流也可以由具有共源共栅降低的输入阻抗和共源共栅增加的输出阻抗的调节共源共栅缓冲器接收和缓冲。