公开(公告)号：US20100140610A1

公开(公告)日：2010-06-10

申请号：US12556277

申请日：2009-09-09

申请人： Young-Wook Lee ,  Hong-Suk Yoo ,  Jean-Ho Song ,  Jae-Hyoung Youn ,  Woo-Geun Lee ,  Ki-Won Kim ,  Jang-In Kim

发明人： Young-Wook Lee ,  Hong-Suk Yoo ,  Jean-Ho Song ,  Jae-Hyoung Youn ,  Woo-Geun Lee ,  Ki-Won Kim ,  Jang-In Kim

IPC分类号： H01L29/786 ,  H01L29/12 ,  H01L21/336

CPC分类号： H01L29/66742 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248

摘要： A thin film transistor substrate according to an embodiment of the present invention includes: an insulation substrate; a gate line formed on the insulation substrate; a first interlayer insulating layer formed on the gate line; a data line and a gate electrode formed on the first interlayer insulating layer; a gate insulating layer formed on the data line and gate electrode; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; a second interlayer insulating layer formed on the semiconductor; a first connection formed on the second interlayer insulating layer and electrically connecting the gate line and the gate electrode to each other; a drain electrode connected to the semiconductor; a pixel electrode connected to the drain electrode; and a second connection connecting the data line and the semiconductor to each other.

摘要翻译： 根据本发明实施例的薄膜晶体管基板包括：绝缘基板; 形成在所述绝缘基板上的栅极线; 形成在栅极线上的第一层间绝缘层; 形成在所述第一层间绝缘层上的数据线和栅电极; 形成在数据线和栅电极上的栅极绝缘层; 形成在栅极绝缘层上并与栅电极重叠的半导体; 形成在所述半导体上的第二层间绝缘层; 形成在所述第二层间绝缘层上并将所述栅极线和所述栅电极彼此电连接的第一连接; 连接到半导体的漏电极; 连接到所述漏电极的像素电极; 以及将数据线和半导体彼此连接的第二连接。

公开(公告)号：US08174020B2

公开(公告)日：2012-05-08

申请号：US12556277

申请日：2009-09-09

申请人： Young-Wook Lee ,  Hong-Suk Yoo ,  Jean-Ho Song ,  Jae-Hyoung Youn ,  Woo-Geun Lee ,  Ki-Won Kim ,  Jong-In Kim

发明人： Young-Wook Lee ,  Hong-Suk Yoo ,  Jean-Ho Song ,  Jae-Hyoung Youn ,  Woo-Geun Lee ,  Ki-Won Kim ,  Jong-In Kim

IPC分类号： H01L27/14

CPC分类号： H01L29/66742 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248

摘要： A thin film transistor substrate according to an embodiment of the present invention includes: an insulation substrate; a gate line formed on the insulation substrate; a first interlayer insulating layer formed on the gate line; a data line and a gate electrode formed on the first interlayer insulating layer; a gate insulating layer formed on the data line and gate electrode; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; a second interlayer insulating layer formed on the semiconductor; a first connection formed on the second interlayer insulating layer and electrically connecting the gate line and the gate electrode to each other; a drain electrode connected to the semiconductor; a pixel electrode connected to the drain electrode; and a second connection connecting the data line and the semiconductor to each other.

摘要翻译： 根据本发明实施例的薄膜晶体管基板包括：绝缘基板; 形成在所述绝缘基板上的栅极线; 形成在栅极线上的第一层间绝缘层; 形成在所述第一层间绝缘层上的数据线和栅电极; 形成在数据线和栅电极上的栅极绝缘层; 形成在栅极绝缘层上并与栅电极重叠的半导体; 形成在所述半导体上的第二层间绝缘层; 形成在所述第二层间绝缘层上并将所述栅极线和所述栅电极彼此电连接的第一连接; 连接到半导体的漏电极; 连接到所述漏电极的像素电极; 以及将数据线和半导体彼此连接的第二连接。

公开(公告)号：US20120193634A1

公开(公告)日：2012-08-02

申请号：US13444768

申请日：2012-04-11

申请人： Young-Wook Lee ,  Hong-Suk Yoo ,  Jean-Ho Song ,  Jae-Hyoung Youn ,  Woo-Geun Lee ,  Ki-Won Kim ,  Jong-In Kim

发明人： Young-Wook Lee ,  Hong-Suk Yoo ,  Jean-Ho Song ,  Jae-Hyoung Youn ,  Woo-Geun Lee ,  Ki-Won Kim ,  Jong-In Kim

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/66742 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248

摘要： A thin film transistor substrate according to an embodiment of the present invention includes: an insulation substrate; a gate line formed on the insulation substrate; a first interlayer insulating layer formed on the gate line; a data line and a gate electrode formed on the first interlayer insulating layer; a gate insulating layer formed on the data line and gate electrode; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; a second interlayer insulating layer formed on the semiconductor; a first connection formed on the second interlayer insulating layer and electrically connecting the gate line and the gate electrode to each other; a drain electrode connected to the semiconductor; a pixel electrode connected to the drain electrode; and a second connection connecting the data line and the semiconductor to each other.

摘要翻译： 根据本发明实施例的薄膜晶体管基板包括：绝缘基板; 形成在所述绝缘基板上的栅极线; 形成在栅极线上的第一层间绝缘层; 形成在所述第一层间绝缘层上的数据线和栅电极; 形成在数据线和栅电极上的栅极绝缘层; 形成在栅极绝缘层上并与栅电极重叠的半导体; 形成在所述半导体上的第二层间绝缘层; 形成在所述第二层间绝缘层上并将所述栅极线和所述栅电极彼此电连接的第一连接; 连接到半导体的漏电极; 连接到所述漏电极的像素电极; 以及将数据线和半导体彼此连接的第二连接。

公开(公告)号：US08389998B2

公开(公告)日：2013-03-05

申请号：US13444768

申请日：2012-04-11

申请人： Young-Wook Lee ,  Hong-Suk Yoo ,  Jean-Ho Song ,  Jae-Hyoung Youn ,  Woo-Geun Lee ,  Ki-Won Kim ,  Jong-In Kim

发明人： Young-Wook Lee ,  Hong-Suk Yoo ,  Jean-Ho Song ,  Jae-Hyoung Youn ,  Woo-Geun Lee ,  Ki-Won Kim ,  Jong-In Kim

IPC分类号： H01L27/14

CPC分类号： H01L29/66742 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248

摘要： A thin film transistor substrate according to an embodiment of the present invention includes: an insulation substrate; a gate line formed on the insulation substrate; a first interlayer insulating layer formed on the gate line; a data line and a gate electrode formed on the first interlayer insulating layer; a gate insulating layer formed on the data line and gate electrode; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; a second interlayer insulating layer formed on the semiconductor; a first connection formed on the second interlayer insulating layer and electrically connecting the gate line and the gate electrode to each other; a drain electrode connected to the semiconductor; a pixel electrode connected to the drain electrode; and a second connection connecting the data line and the semiconductor to each other.

摘要翻译： 根据本发明实施例的薄膜晶体管基板包括：绝缘基板; 形成在所述绝缘基板上的栅极线; 形成在栅极线上的第一层间绝缘层; 形成在所述第一层间绝缘层上的数据线和栅电极; 形成在数据线和栅电极上的栅极绝缘层; 形成在栅极绝缘层上并与栅电极重叠的半导体; 形成在所述半导体上的第二层间绝缘层; 形成在所述第二层间绝缘层上并将所述栅极线和所述栅电极彼此电连接的第一连接; 连接到半导体的漏电极; 连接到所述漏电极的像素电极; 以及将数据线和半导体彼此连接的第二连接。

公开(公告)号：US08058114B2

公开(公告)日：2011-11-15

申请号：US12797527

申请日：2010-06-09

申请人： Jang-Soo Kim ,  Hong-Long Ning ,  Bong-Kyun Kim ,  Hong-Sick Park ,  Shi-Yul Kim ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Jae-Hyoung Youn ,  Woo-Geun Lee ,  Yang-Ho Bae ,  Pil-Sang Yun ,  Jong-Hyun Choung ,  Sun-Young Hong ,  Ki-Won Kim ,  Byeong-Jin Lee ,  Young-Wook Lee ,  Jong-In Kim ,  Byeong-Beom Kim ,  Nam-Seok Suh

发明人： Jang-Soo Kim ,  Hong-Long Ning ,  Bong-Kyun Kim ,  Hong-Sick Park ,  Shi-Yul Kim ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Jae-Hyoung Youn ,  Woo-Geun Lee ,  Yang-Ho Bae ,  Pil-Sang Yun ,  Jong-Hyun Choung ,  Sun-Young Hong ,  Ki-Won Kim ,  Byeong-Jin Lee ,  Young-Wook Lee ,  Jong-In Kim ,  Byeong-Beom Kim ,  Nam-Seok Suh

IPC分类号： H01L21/84 ,  H01L21/336

CPC分类号： G02F1/13458 ,  G02F1/136286 ,  G02F2001/136295 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1288

摘要： A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.

摘要翻译： 栅极线包括形成在基底基板上的第一籽晶层和形成在第一籽晶层上的第一金属层。 在基底基板上形成第一绝缘层。 在基底基板上形成第二绝缘层。 这里，在与栅极线交叉的方向上通过第二绝缘层形成线沟槽。 数据线包括形成在线沟槽下方的第二晶种层和形成在线沟槽中的第二金属层。 像素电极形成在基底基板的像素区域中。 因此，使用绝缘层形成预定深度的沟槽，并且通过电镀方法形成金属层，从而可以形成具有足够厚度的金属线。

公开(公告)号：US20100261322A1

公开(公告)日：2010-10-14

申请号：US12797527

申请日：2010-06-09

申请人： Jang-Soo Kim ,  Hong-Long Ning ,  Bong-Kyun Kim ,  Hong-Sick Park ,  Shi-Yul Kim ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Jae-Hyoung Youn ,  Woo-Geun Lee ,  Yang-Ho Bae ,  Pil-Sang Yun ,  Jong-Hyun Choung ,  Sun-Young Hong ,  Ki-Won Kim ,  Byeong-Jin Lee ,  Young-Wook Lee ,  Jong-In Kim ,  Byeong-Beom Kim ,  Nam-Seok Suh

发明人： Jang-Soo Kim ,  Hong-Long Ning ,  Bong-Kyun Kim ,  Hong-Sick Park ,  Shi-Yul Kim ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Jae-Hyoung Youn ,  Woo-Geun Lee ,  Yang-Ho Bae ,  Pil-Sang Yun ,  Jong-Hyun Choung ,  Sun-Young Hong ,  Ki-Won Kim ,  Byeong-Jin Lee ,  Young-Wook Lee ,  Jong-In Kim ,  Byeong-Beom Kim ,  Nam-Seok Suh

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： G02F1/13458 ,  G02F1/136286 ,  G02F2001/136295 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1288

摘要： A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.

摘要翻译： 栅极线包括形成在基底基板上的第一籽晶层和形成在第一籽晶层上的第一金属层。 在基底基板上形成第一绝缘层。 在基底基板上形成第二绝缘层。 这里，在与栅极线交叉的方向上通过第二绝缘层形成线沟槽。 数据线包括形成在线沟槽下方的第二晶种层和形成在线沟槽中的第二金属层。 像素电极形成在基底基板的像素区域中。 因此，使用绝缘层形成预定深度的沟槽，并且通过电镀方法形成金属层，从而可以形成具有足够厚度的金属线。

公开(公告)号：US08723179B2

公开(公告)日：2014-05-13

申请号：US12957743

申请日：2010-12-01

申请人： Pil-Sang Yun ,  Ki-Won Kim ,  Hye-Young Ryu ,  Woo-Geun Lee ,  Seung-Ha Choi ,  Jae-Hyoung Youn ,  Kyoung-Jae Chung ,  Young-Wook Lee ,  Je-Hun Lee ,  Kap-Soo Yoon ,  Do-Hyun Kim ,  Dong-Ju Yang ,  Young-Joo Choi

发明人： Pil-Sang Yun ,  Ki-Won Kim ,  Hye-Young Ryu ,  Woo-Geun Lee ,  Seung-Ha Choi ,  Jae-Hyoung Youn ,  Kyoung-Jae Chung ,  Young-Wook Lee ,  Je-Hun Lee ,  Kap-Soo Yoon ,  Do-Hyun Kim ,  Dong-Ju Yang ,  Young-Joo Choi

IPC分类号： H01L29/04 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

CPC分类号： H01L29/41733 ,  H01L21/44 ,  H01L21/441 ,  H01L21/465 ,  H01L21/475 ,  H01L21/47573 ,  H01L21/47635 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696

摘要： A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

摘要翻译： 薄膜晶体管面板包括绝缘基板，设置在绝缘基板上的栅极绝缘层，设置在栅极绝缘层上的氧化物半导体层，设置在氧化物半导体层上的蚀刻停止器，以及设置在源极电极和漏极上的 在蚀刻停止器上。

公开(公告)号：US08604469B2

公开(公告)日：2013-12-10

申请号：US12464920

申请日：2009-05-13

申请人： Woo-Geun Lee ,  Jae-Hyoung Youn ,  Ki-Won Kim ,  Young-Wook Lee ,  Jong-In Kim

发明人： Woo-Geun Lee ,  Jae-Hyoung Youn ,  Ki-Won Kim ,  Young-Wook Lee ,  Jong-In Kim

IPC分类号： H01L29/10

CPC分类号： H01L29/7869 ,  H01L27/1225 ,  H01L29/78696

摘要： A thin film transistor array panel includes a substrate, a gate line formed on the substrate and including a gate electrode, a gate insulating layer formed on the gate line, a semiconductor formed on the gate insulating layer and including a channel of a thin film transistor, a data line formed on the semiconductor and including a source electrode and a drain electrode formed on the semiconductor and opposite to the source electrode with respect to the channel of the thin film transistor, wherein the channel of the thin film transistor covers both side surfaces of the gate electrode.

摘要翻译： 薄膜晶体管阵列面板包括基板，形成在基板上的栅极线，包括栅极电极，形成在栅极线上的栅极绝缘层，形成在栅极绝缘层上并包括薄膜晶体管的沟道的半导体 ，形成在半导体上的数据线，包括相对于薄膜晶体管的沟道形成在半导体上并与源电极相对的源电极和漏电极，其中薄膜晶体管的沟道覆盖两个侧表面 的栅电极。

公开(公告)号：US07759738B2

公开(公告)日：2010-07-20

申请号：US12269748

申请日：2008-11-12

申请人： Jang-Soo Kim ,  Hong-Long Ning ,  Bong-Kyun Kim ,  Hong-Sick Park ,  Shi-Yul Kim ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Jae-Hyoung Youn ,  Woo-Geun Lee ,  Yang-Ho Bae ,  Pil-Sang Yun ,  Jong-Hyun Choung ,  Sun-Young Hong ,  Ki-Won Kim ,  Byeong-Jin Lee ,  Young-Wook Lee ,  Jong-In Kim ,  Byeong-Beom Kim ,  Nam-Seok Suh

发明人： Jang-Soo Kim ,  Hong-Long Ning ,  Bong-Kyun Kim ,  Hong-Sick Park ,  Shi-Yul Kim ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Jae-Hyoung Youn ,  Woo-Geun Lee ,  Yang-Ho Bae ,  Pil-Sang Yun ,  Jong-Hyun Choung ,  Sun-Young Hong ,  Ki-Won Kim ,  Byeong-Jin Lee ,  Young-Wook Lee ,  Jong-In Kim ,  Byeong-Beom Kim ,  Nam-Seok Suh

IPC分类号： H01L29/04 ,  H01L29/10 ,  H01L29/15

CPC分类号： G02F1/13458 ,  G02F1/136286 ,  G02F2001/136295 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1288

摘要： A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.

摘要翻译： 栅极线包括形成在基底基板上的第一籽晶层和形成在第一籽晶层上的第一金属层。 在基底基板上形成第一绝缘层。 在基底基板上形成第二绝缘层。 这里，在与栅极线交叉的方向上通过第二绝缘层形成线沟槽。 数据线包括形成在线沟槽下方的第二晶种层和形成在线沟槽中的第二金属层。 像素电极形成在基底基板的像素区域中。 因此，使用绝缘层形成预定深度的沟槽，并且通过电镀方法形成金属层，从而可以形成具有足够厚度的金属线。

公开(公告)号：US07834676B2

公开(公告)日：2010-11-16

申请号：US12357261

申请日：2009-01-21

申请人： Woo-Geun Lee ,  Jean-Ho Song ,  Yeong-Keun Kwon ,  Min-Cheol Lee ,  Ki-Won Kim ,  Young-Wook Lee

发明人： Woo-Geun Lee ,  Jean-Ho Song ,  Yeong-Keun Kwon ,  Min-Cheol Lee ,  Ki-Won Kim ,  Young-Wook Lee

IPC分类号： G11C11/34

CPC分类号： G09G3/3648 ,  G09G2300/0413 ,  G09G2300/0819 ,  G09G2320/043

摘要： A device for accounting for changes in characteristics of a transistor is presented. The device includes a transistor and a comparator receiving a feedback signal from the transistor and a reference signal. The comparator provides an output to a bias voltage generator. The bias voltage generator includes an input connected to the output of the comparator and an output connected to the transistor. In some embodiments of the invention the transistor is a double gate transistor and the bias voltage generator is applied to a top gate of the double gate transistor in order to control characteristics of the transistor such as turn on voltage.

摘要翻译： 提出了一种用于考虑晶体管特性变化的装置。 该器件包括晶体管和比较器，其接收来自晶体管的反馈信号和参考信号。 比较器向偏置电压发生器提供输出。 偏置电压发生器包括连接到比较器的输出的输入端和连接到晶体管的输出。 在本发明的一些实施例中，晶体管是双栅极晶体管，并且偏置电压发生器被施加到双栅晶体管的顶栅，以便控制晶体管的特性，例如导通电压。