公开(公告)号：US07358827B2

公开(公告)日：2008-04-15

申请号：US11487545

申请日：2006-07-14

申请人： Young-soo Sohn ,  Jae-hyung Lee

发明人： Young-soo Sohn ,  Jae-hyung Lee

IPC分类号： H03L7/093

CPC分类号： H03L7/107 ,  H03L7/081 ,  H03L7/0893 ,  H03L7/0895 ,  H03L7/093

摘要： A process-insensitive self-biasing PLL circuit and self-biasing method thereof prevent deterioration of loop stability even when there is a fabrication process variation. The self-biasing PLL circuit includes a phase frequency detector, a main charge pump circuit, an auxiliary charge pump circuit, a first operational amplifier, a second operational amplifier, a voltage-controlled oscillator, a divider, and a bias circuit. In the self-biasing PLL circuit, the first operational amplifier amplifies the voltage of a loop filter capacitor and the second operational amplifier serving as a regulator amplifies the output voltage of the first operational amplifier. The output voltage of the second operational amplifier is used as a control voltage of the voltage-controlled oscillator. Particularly, the bias circuit generates a first bias current using an NMOS transistor, generates a second bias current using a PMOS transistor, and sums up the first and second bias currents to generate a third bias current in response to the output voltage of the second operational amplifier. The first bias current is provided to the main charge pump circuit and the auxiliary charge pump circuit as their bias currents, and the third bias current is provided to the first operational amplifier as its bias current.

摘要翻译： 不敏感的自偏置PLL电路及其自偏置方法即使在存在制造工艺变化时也防止环路稳定性的恶化。 自偏置PLL电路包括相位频率检测器，主电荷泵电路，辅助电荷泵电路，第一运算放大器，第二运算放大器，压控振荡器，分频器和偏置电路。 在自偏置PLL电路中，第一运算放大器放大环路滤波电容器的电压，并且用作调节器的第二运算放大器放大第一运算放大器的输出电压。 第二运算放大器的输出电压用作压控振荡器的控制电压。 特别地，偏置电路使用NMOS晶体管产生第一偏置电流，使用PMOS晶体管产生第二偏置电流，并且对第一和第二偏置电流求和以响应于第二操作的输出电压产生第三偏置电流 放大器 将第一偏置电流作为其偏置电流提供给主电荷泵电路和辅助电荷泵电路，并且将第三偏置电流作为其偏置电流提供给第一运算放大器。

公开(公告)号：US20070018736A1

公开(公告)日：2007-01-25

申请号：US11487545

申请日：2006-07-14

申请人： Young-soo Sohn ,  Jae-hyung Lee

发明人： Young-soo Sohn ,  Jae-hyung Lee

IPC分类号： H03L7/00

CPC分类号： H03L7/107 ,  H03L7/081 ,  H03L7/0893 ,  H03L7/0895 ,  H03L7/093

摘要： A process-insensitive self-biasing PLL circuit and self-biasing method thereof prevent deterioration of loop stability even when there is a fabrication process variation. The self-biasing PLL circuit includes a phase frequency detector, a main charge pump circuit, an auxiliary charge pump circuit, a first operational amplifier, a second operational amplifier, a voltage-controlled oscillator, a divider, and a bias circuit. In the self-biasing PLL circuit, the first operational amplifier amplifies the voltage of a loop filter capacitor and the second operational amplifier serving as a regulator amplifies the output voltage of the first operational amplifier. The output voltage of the second operational amplifier is used as a control voltage of the voltage-controlled oscillator. Particularly, the bias circuit generates a first bias current using an NMOS transistor, generates a second bias current using a PMOS transistor, and sums up the first and second bias currents to generate a third bias current in response to the output voltage of the second operational amplifier. The first bias current is provided to the main charge pump circuit and the auxiliary charge pump circuit as their bias currents, and the third bias current is provided to the first operational amplifier as its bias current.

摘要翻译： 不敏感的自偏置PLL电路及其自偏置方法即使在存在制造工艺变化时也防止环路稳定性的恶化。 自偏置PLL电路包括相位频率检测器，主电荷泵电路，辅助电荷泵电路，第一运算放大器，第二运算放大器，压控振荡器，分频器和偏置电路。 在自偏置PLL电路中，第一运算放大器放大环路滤波电容器的电压，并且用作调节器的第二运算放大器放大第一运算放大器的输出电压。 第二运算放大器的输出电压用作压控振荡器的控制电压。 特别地，偏置电路使用NMOS晶体管产生第一偏置电流，使用PMOS晶体管产生第二偏置电流，并且对第一和第二偏置电流求和以响应于第二操作的输出电压产生第三偏置电流 放大器 将第一偏置电流作为其偏置电流提供给主电荷泵电路和辅助电荷泵电路，并且将第三偏置电流作为其偏置电流提供给第一运算放大器。

公开(公告)号：US06954094B2

公开(公告)日：2005-10-11

申请号：US10645018

申请日：2003-08-21

申请人： Jae-hyung Lee ,  Kyu-hyoun Kim

发明人： Jae-hyung Lee ,  Kyu-hyoun Kim

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/407 ,  G11C11/4076 ,  H03K5/13 ,  H03L7/06

CPC分类号： G11C7/1066 ,  G11C7/1045 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

摘要： A semiconductor memory device having a partially controlled delay locked loop includes a delay locked loop and a control signal generator. The control signal generator generates a first control signal and a second control signal, which are responsive to first through fifth mode selection signals for selecting operation modes of the semiconductor memory, device to partially turn the delay locked loop on or off. If the first control signal or the second control signal is activated, a portion of the delay locked loop to which the first or second control signal is applied is turned off. If the first control signal or the second control signal is deactivated, a portion of the delay locked loop to which the first or second control signal is applied is turned on. If the first mode selection signal is activated, only the second control signal is activated. If the second mode selection signal is activated, the first and second control signals are deactivated. If at least one of the third through fifth mode selection signals is activated, the first and second control signals are activated. Since the semiconductor memory device includes a built-in delay locked loop which is partially turned on or off, current consumption of the semiconductor memory device can be reduced.

摘要翻译： 具有部分控制的延迟锁定环路的半导体存储器件包括延迟锁定环路和控制信号发生器。 所述控制信号发生器产生第一控制信号和第二控制信号，所述第一控制信号和第二控制信号响应于第一至第五模式选择信号，用于选择半导体存储器的操作模式，以部分地将延迟锁定环打开或关闭。 如果第一控制信号或第二控制信号被激活，则施加第一或第二控制信号的延迟锁定环路的一部分被关闭。 如果第一控制信号或第二控制信号被去激活，则施加第一或第二控制信号的延迟锁定环路的一部分被接通。 如果第一模式选择信号被激活，则只有第二控制信号被激活。 如果第二模式选择信号被激活，则第一和第二控制信号被去激活。 如果第三至第五模式选择信号中的至少一个被激活，则第一和第二控制信号被激活。 由于半导体存储器件包括部分导通或截止的内置延迟锁定环，所以可以减少半导体存储器件的电流消耗。

公开(公告)号：US20050017783A1

公开(公告)日：2005-01-27

申请号：US10890493

申请日：2004-07-13

申请人： Jae-hyung Lee ,  Kyu-hyoun Kim

发明人： Jae-hyung Lee ,  Kyu-hyoun Kim

IPC分类号： H03K5/02 ,  H03K3/356 ,  H03K19/003 ,  H03K19/0185 ,  H04L25/02 ,  H04L25/45 ,  H03K3/037

CPC分类号： H04L25/45 ,  H03K3/356104 ,  H03K3/356113 ,  H03K19/00323 ,  H03K19/018521

摘要： Provided are an interface circuit and a signal clamping circuit using a level-down shifter. The interface circuit includes the level-down shifter between a first power circuit driven by a first power and a second power circuit driven by a second power. The level-down shifter converts an output of the first power circuit that has a voltage level of the first power into an output of a voltage level of the second power. The level-down shifter includes a first circuit unit, a second circuit unit, a third circuit unit, and a fourth circuit unit. The first circuit unit is driven by the first power and receives the output of the first power circuit. The second circuit unit is driven by the second power and receives the output of the first power circuit. The third circuit unit is driven by the second power and receives the output of the first power circuit. The fourth circuit unit is driven by the second power, receives an output of the third circuit unit, and is connected to an output of the second circuit unit.

摘要翻译： 提供了使用电平降低移位器的接口电路和信号钳位电路。 接口电路包括由第一电源驱动的第一电源电路和由第二电源驱动的第二电源电路之间的电平降低移位器。 电平降低移位器将具有第一功率的电压电平的第一电源电路的输出转换为第二功率的电压电平的输出。 电平降低移位器包括第一电路单元，第二电路单元，第三电路单元和第四电路单元。 第一电路单元由第一电源驱动并接收第一电源电路的输出。 第二电路单元由第二电源驱动并接收第一电源电路的输出。 第三电路单元由第二电源驱动并接收第一电源电路的输出。 第四电路单元由第二电源驱动，接收第三电路单元的输出，并连接到第二电路单元的输出端。

公开(公告)号：US20070146043A1

公开(公告)日：2007-06-28

申请号：US11679375

申请日：2007-02-27

申请人： Jae-hyung Lee ,  Kyu-hyoun Kim

发明人： Jae-hyung Lee ,  Kyu-hyoun Kim

IPC分类号： H03L5/00

CPC分类号： H04L25/45 ,  H03K3/356104 ,  H03K3/356113 ,  H03K19/00323 ,  H03K19/018521

摘要： Provided are an interface circuit and a signal clamping circuit using a level-down shifter. The interface circuit includes the level-down shifter between a first power circuit driven by a first power and a second power circuit driven by a second power. The level-down shifter converts an output of the first power circuit that has a voltage level of the first power into an output of a voltage level of the second power. The level-down shifter includes a first circuit unit, a second circuit unit, a third circuit unit, and a fourth circuit unit. The first circuit unit is driven by the first power and receives the output of the first power circuit. The second circuit unit is driven by the second power and receives the output of the first power circuit. The third circuit unit is driven by the second power and receives the output of the first power circuit. The fourth circuit unit is driven by the second power, receives an output of the third circuit unit, and is connected to an output of the second circuit unit.

摘要翻译： 提供了使用电平降低移位器的接口电路和信号钳位电路。 接口电路包括由第一电源驱动的第一电源电路和由第二电源驱动的第二电源电路之间的电平降低移位器。 电平降低移位器将具有第一功率的电压电平的第一电源电路的输出转换为第二功率的电压电平的输出。 电平降低移位器包括第一电路单元，第二电路单元，第三电路单元和第四电路单元。 第一电路单元由第一电源驱动并接收第一电源电路的输出。 第二电路单元由第二电源驱动并接收第一电源电路的输出。 第三电路单元由第二电源驱动并接收第一电源电路的输出。 第四电路单元由第二电源驱动，接收第三电路单元的输出，并连接到第二电路单元的输出端。

公开(公告)号：US20070139093A1

公开(公告)日：2007-06-21

申请号：US11679519

申请日：2007-02-27

申请人： Jae-hyung Lee ,  Kyu-hyoun Kim

发明人： Jae-hyung Lee ,  Kyu-hyoun Kim

IPC分类号： H03L5/00

CPC分类号： H04L25/45 ,  H03K3/356104 ,  H03K3/356113 ,  H03K19/00323 ,  H03K19/018521

摘要： Provided are an interface circuit and a signal clamping circuit using a level-down shifter. The interface circuit includes the level-down shifter between a first power circuit driven by a first power and a second power circuit driven by a second power. The level-down shifter converts an output of the first power circuit that has a voltage level of the first power into an output of a voltage level of the second power. The level-down shifter includes a first circuit unit, a second circuit unit, a third circuit unit, and a fourth circuit unit. The first circuit unit is driven by the first power and receives the output of the first power circuit. The second circuit unit is driven by the second power and receives the output of the first power circuit. The third circuit unit is driven by the second power and receives the output of the first power circuit. The fourth circuit unit is driven by the second power, receives an output of the third circuit unit, and is connected to an output of the second circuit unit.

公开(公告)号：US07190206B2

公开(公告)日：2007-03-13

申请号：US10890493

申请日：2004-07-13

申请人： Jae-hyung Lee ,  Kyu-hyoun Kim

发明人： Jae-hyung Lee ,  Kyu-hyoun Kim

IPC分类号： H03L5/00

CPC分类号： H04L25/45 ,  H03K3/356104 ,  H03K3/356113 ,  H03K19/00323 ,  H03K19/018521

摘要： Provided are an interface circuit and a signal clamping circuit using a level-down shifter. The interface circuit includes the level-down shifter between a first power circuit driven by a first power and a second power circuit driven by a second power. The level-down shifter converts an output of the first power circuit that has a voltage level of the first power into an output of a voltage level of the second power. The level-down shifter includes a first circuit unit, a second circuit unit, a third circuit unit, and a fourth circuit unit. The first circuit unit is driven by the first power and receives the output of the first power circuit. The second circuit unit is driven by the second power and receives the output of the first power circuit. The third circuit unit is driven by the second power and receives the output of the first power circuit. The fourth circuit unit is driven by the second power, receives an output of the third circuit unit, and is connected to an output of the second circuit unit.

摘要翻译： 提供了使用电平降低移位器的接口电路和信号钳位电路。 接口电路包括由第一电源驱动的第一电源电路和由第二电源驱动的第二电源电路之间的电平降低移位器。 电平降低移位器将具有第一功率的电压电平的第一电源电路的输出转换为第二功率的电压电平的输出。 电平降低移位器包括第一电路单元，第二电路单元，第三电路单元和第四电路单元。 第一电路单元由第一电源驱动并接收第一电源电路的输出。 第二电路单元由第二电源驱动并接收第一电源电路的输出。 第三电路单元由第二电源驱动并接收第一电源电路的输出。 第四电路单元由第二电源驱动，接收第三电路单元的输出，并连接到第二电路单元的输出端。