公开(公告)号：US06954094B2

公开(公告)日：2005-10-11

申请号：US10645018

申请日：2003-08-21

申请人： Jae-hyung Lee ,  Kyu-hyoun Kim

发明人： Jae-hyung Lee ,  Kyu-hyoun Kim

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/407 ,  G11C11/4076 ,  H03K5/13 ,  H03L7/06

CPC分类号： G11C7/1066 ,  G11C7/1045 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

摘要： A semiconductor memory device having a partially controlled delay locked loop includes a delay locked loop and a control signal generator. The control signal generator generates a first control signal and a second control signal, which are responsive to first through fifth mode selection signals for selecting operation modes of the semiconductor memory, device to partially turn the delay locked loop on or off. If the first control signal or the second control signal is activated, a portion of the delay locked loop to which the first or second control signal is applied is turned off. If the first control signal or the second control signal is deactivated, a portion of the delay locked loop to which the first or second control signal is applied is turned on. If the first mode selection signal is activated, only the second control signal is activated. If the second mode selection signal is activated, the first and second control signals are deactivated. If at least one of the third through fifth mode selection signals is activated, the first and second control signals are activated. Since the semiconductor memory device includes a built-in delay locked loop which is partially turned on or off, current consumption of the semiconductor memory device can be reduced.

摘要翻译： 具有部分控制的延迟锁定环路的半导体存储器件包括延迟锁定环路和控制信号发生器。 所述控制信号发生器产生第一控制信号和第二控制信号，所述第一控制信号和第二控制信号响应于第一至第五模式选择信号，用于选择半导体存储器的操作模式，以部分地将延迟锁定环打开或关闭。 如果第一控制信号或第二控制信号被激活，则施加第一或第二控制信号的延迟锁定环路的一部分被关闭。 如果第一控制信号或第二控制信号被去激活，则施加第一或第二控制信号的延迟锁定环路的一部分被接通。 如果第一模式选择信号被激活，则只有第二控制信号被激活。 如果第二模式选择信号被激活，则第一和第二控制信号被去激活。 如果第三至第五模式选择信号中的至少一个被激活，则第一和第二控制信号被激活。 由于半导体存储器件包括部分导通或截止的内置延迟锁定环，所以可以减少半导体存储器件的电流消耗。

公开(公告)号：US20050017783A1

公开(公告)日：2005-01-27

申请号：US10890493

申请日：2004-07-13

申请人： Jae-hyung Lee ,  Kyu-hyoun Kim

发明人： Jae-hyung Lee ,  Kyu-hyoun Kim

IPC分类号： H03K5/02 ,  H03K3/356 ,  H03K19/003 ,  H03K19/0185 ,  H04L25/02 ,  H04L25/45 ,  H03K3/037

CPC分类号： H04L25/45 ,  H03K3/356104 ,  H03K3/356113 ,  H03K19/00323 ,  H03K19/018521

摘要： Provided are an interface circuit and a signal clamping circuit using a level-down shifter. The interface circuit includes the level-down shifter between a first power circuit driven by a first power and a second power circuit driven by a second power. The level-down shifter converts an output of the first power circuit that has a voltage level of the first power into an output of a voltage level of the second power. The level-down shifter includes a first circuit unit, a second circuit unit, a third circuit unit, and a fourth circuit unit. The first circuit unit is driven by the first power and receives the output of the first power circuit. The second circuit unit is driven by the second power and receives the output of the first power circuit. The third circuit unit is driven by the second power and receives the output of the first power circuit. The fourth circuit unit is driven by the second power, receives an output of the third circuit unit, and is connected to an output of the second circuit unit.

摘要翻译： 提供了使用电平降低移位器的接口电路和信号钳位电路。 接口电路包括由第一电源驱动的第一电源电路和由第二电源驱动的第二电源电路之间的电平降低移位器。 电平降低移位器将具有第一功率的电压电平的第一电源电路的输出转换为第二功率的电压电平的输出。 电平降低移位器包括第一电路单元，第二电路单元，第三电路单元和第四电路单元。 第一电路单元由第一电源驱动并接收第一电源电路的输出。 第二电路单元由第二电源驱动并接收第一电源电路的输出。 第三电路单元由第二电源驱动并接收第一电源电路的输出。 第四电路单元由第二电源驱动，接收第三电路单元的输出，并连接到第二电路单元的输出端。

公开(公告)号：US07190206B2

公开(公告)日：2007-03-13

申请号：US10890493

申请日：2004-07-13

申请人： Jae-hyung Lee ,  Kyu-hyoun Kim

发明人： Jae-hyung Lee ,  Kyu-hyoun Kim

IPC分类号： H03L5/00

CPC分类号： H04L25/45 ,  H03K3/356104 ,  H03K3/356113 ,  H03K19/00323 ,  H03K19/018521

摘要： Provided are an interface circuit and a signal clamping circuit using a level-down shifter. The interface circuit includes the level-down shifter between a first power circuit driven by a first power and a second power circuit driven by a second power. The level-down shifter converts an output of the first power circuit that has a voltage level of the first power into an output of a voltage level of the second power. The level-down shifter includes a first circuit unit, a second circuit unit, a third circuit unit, and a fourth circuit unit. The first circuit unit is driven by the first power and receives the output of the first power circuit. The second circuit unit is driven by the second power and receives the output of the first power circuit. The third circuit unit is driven by the second power and receives the output of the first power circuit. The fourth circuit unit is driven by the second power, receives an output of the third circuit unit, and is connected to an output of the second circuit unit.

摘要翻译： 提供了使用电平降低移位器的接口电路和信号钳位电路。 接口电路包括由第一电源驱动的第一电源电路和由第二电源驱动的第二电源电路之间的电平降低移位器。 电平降低移位器将具有第一功率的电压电平的第一电源电路的输出转换为第二功率的电压电平的输出。 电平降低移位器包括第一电路单元，第二电路单元，第三电路单元和第四电路单元。 第一电路单元由第一电源驱动并接收第一电源电路的输出。 第二电路单元由第二电源驱动并接收第一电源电路的输出。 第三电路单元由第二电源驱动并接收第一电源电路的输出。 第四电路单元由第二电源驱动，接收第三电路单元的输出，并连接到第二电路单元的输出端。

公开(公告)号：US20070146043A1

公开(公告)日：2007-06-28

申请号：US11679375

申请日：2007-02-27

申请人： Jae-hyung Lee ,  Kyu-hyoun Kim

发明人： Jae-hyung Lee ,  Kyu-hyoun Kim

IPC分类号： H03L5/00

CPC分类号： H04L25/45 ,  H03K3/356104 ,  H03K3/356113 ,  H03K19/00323 ,  H03K19/018521

摘要： Provided are an interface circuit and a signal clamping circuit using a level-down shifter. The interface circuit includes the level-down shifter between a first power circuit driven by a first power and a second power circuit driven by a second power. The level-down shifter converts an output of the first power circuit that has a voltage level of the first power into an output of a voltage level of the second power. The level-down shifter includes a first circuit unit, a second circuit unit, a third circuit unit, and a fourth circuit unit. The first circuit unit is driven by the first power and receives the output of the first power circuit. The second circuit unit is driven by the second power and receives the output of the first power circuit. The third circuit unit is driven by the second power and receives the output of the first power circuit. The fourth circuit unit is driven by the second power, receives an output of the third circuit unit, and is connected to an output of the second circuit unit.

摘要翻译： 提供了使用电平降低移位器的接口电路和信号钳位电路。 接口电路包括由第一电源驱动的第一电源电路和由第二电源驱动的第二电源电路之间的电平降低移位器。 电平降低移位器将具有第一功率的电压电平的第一电源电路的输出转换为第二功率的电压电平的输出。 电平降低移位器包括第一电路单元，第二电路单元，第三电路单元和第四电路单元。 第一电路单元由第一电源驱动并接收第一电源电路的输出。 第二电路单元由第二电源驱动并接收第一电源电路的输出。 第三电路单元由第二电源驱动并接收第一电源电路的输出。 第四电路单元由第二电源驱动，接收第三电路单元的输出，并连接到第二电路单元的输出端。

公开(公告)号：US20070139093A1

公开(公告)日：2007-06-21

申请号：US11679519

申请日：2007-02-27

申请人： Jae-hyung Lee ,  Kyu-hyoun Kim

发明人： Jae-hyung Lee ,  Kyu-hyoun Kim

IPC分类号： H03L5/00

CPC分类号： H04L25/45 ,  H03K3/356104 ,  H03K3/356113 ,  H03K19/00323 ,  H03K19/018521

摘要： Provided are an interface circuit and a signal clamping circuit using a level-down shifter. The interface circuit includes the level-down shifter between a first power circuit driven by a first power and a second power circuit driven by a second power. The level-down shifter converts an output of the first power circuit that has a voltage level of the first power into an output of a voltage level of the second power. The level-down shifter includes a first circuit unit, a second circuit unit, a third circuit unit, and a fourth circuit unit. The first circuit unit is driven by the first power and receives the output of the first power circuit. The second circuit unit is driven by the second power and receives the output of the first power circuit. The third circuit unit is driven by the second power and receives the output of the first power circuit. The fourth circuit unit is driven by the second power, receives an output of the third circuit unit, and is connected to an output of the second circuit unit.

公开(公告)号：US08718216B2

公开(公告)日：2014-05-06

申请号：US13242053

申请日：2011-09-23

申请人： Daniel M. Dreps ,  Kyu-hyoun Kim ,  Glen A. Wiedemeier

发明人： Daniel M. Dreps ,  Kyu-hyoun Kim ,  Glen A. Wiedemeier

IPC分类号： H03D3/24

CPC分类号： H04L7/0037 ,  H03L7/0814 ,  H03L7/085 ,  H03L7/089

摘要： An embodiment of the invention comprises a digital phase detector with substantially zero phase offset. The digital phase detector receives a clock signal and a reference clock signal and provides a phase indicator signal to identify whether the clock signal leads or lags the reference clock signal. An embodiment of the invention comprises a method that adds substantially zero phase offset in processing an input clock signal and a delayed clock signal to generate a control signal. The control signal is processed in a variable delay line to generate the delayed clock signal. In an embodiment, a first processor comprises a delay locked loop having a digital phase detector, the digital phase detector comprising a first differential sense amplifier cross-coupled to a second differential sense amplifier, the digital phase detector receiving a clock signal and generating one or more delayed clock signals, a control signal, and a gated data signal.

公开(公告)号：US08639874B2

公开(公告)日：2014-01-28

申请号：US12341515

申请日：2008-12-22

申请人： Warren Edward Maule ,  Kevin C. Gower ,  Kyu-hyoun Kim ,  Dustin James VanStee

发明人： Warren Edward Maule ,  Kevin C. Gower ,  Kyu-hyoun Kim ,  Dustin James VanStee

IPC分类号： G06F12/06

CPC分类号： G11C5/06 ,  G11C5/04 ,  G11C5/14 ,  G11C11/4074

摘要： A computer memory, having one or more of a semiconductor memory device having an internal memory array comprising a plurality of semiconductor dynamic random access memory (DRAM) cells arranged in a matrix of rows and columns, and provided as a memory module rank of such memory devices arranged in an array on a DIMM of one or more of said semiconductor memory device on a substrate which can be coupled via a memory device data interface to a memory system as a memory subsystem, each of said memory device having a low power shut-down state that can be activated using a common memory data interface. Control of power to a DRAM issues over the data interface two commands to a DRAM power control command decode, a power-state program signal and a power-state reset signal as a power-state control commands to control the power state of said DRAM, and to activate for READ/WRITE a memory cell as a normal active or spare device.

摘要翻译： 一种具有一个或多个具有内部存储器阵列的半导体存储器件的计算机存储器，所述内部存储器阵列包括排列成行和列的矩阵的多个半导体动态随机存取存储器（DRAM）单元，并被提供为这种存储器的存储器模块等级 在基板上的一个或多个所述半导体存储器件的DIMM上布置的阵列中的器件，其可以经由存储器件数据接口耦合到作为存储器子系统的存储器系统，每个所述存储器件具有低功率闭合 - 可以使用公共存储器数据接口激活。 通过数据接口对DRAM的功率的控制问题DRAM功率控制命令的两个命令解码，功率状态程序信号和功率状态复位信号作为功率状态控制命令来控制所述DRAM的功率状态， 并激活用于将存储器单元作为正常的有源或备用设备读/写。

公开(公告)号：US20130313705A1

公开(公告)日：2013-11-28

申请号：US13477371

申请日：2012-05-22

申请人： Joab D. Henderson ,  Kyu-hyoun Kim ,  Warren E. Maule ,  Kenneth L. Wright

发明人： Joab D. Henderson ,  Kyu-hyoun Kim ,  Warren E. Maule ,  Kenneth L. Wright

IPC分类号： H01L23/498 ,  H01L21/768

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L23/498 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05027 ,  H01L2224/13014 ,  H01L2224/13021 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/14051 ,  H01L2224/1411 ,  H01L2224/1613 ,  H01L2224/16146 ,  H01L2224/17106 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014

摘要： A method and structures are provided for implementing decoupling capacitors within a DRAM TSV stack. A DRAM is formed with a plurality of TSVs extending completely through the substrate and filled with a conducting material. A layer of glass is grown on both the top and bottom of the DRAM providing an insulator. A layer of metal is grown on each glass layer providing a conductor. The metal and glass layers are etched through to TSVs with a gap provided around the perimeter of via pads. A respective solder ball is formed on the TSVs to connect to another DRAM chip in the DRAM TSV stack. The metal layers are connected to at least one TSV by one respective solder ball and are connected to a voltage source and a dielectric is inserted between the metal layers in the DRAM TSV stack to complete the decoupling capacitor.

摘要翻译： 提供了一种用于在DRAM TSV堆栈内实现去耦电容器的方法和结构。 形成有多个完全延伸穿过衬底并填充有导电材料的TSV的DRAM。 在提供绝缘体的DRAM的顶部和底部都生长玻璃层。 在提供导体的每个玻璃层上生长一层金属。 金属和玻璃层被蚀刻到具有围绕通孔焊盘的周边设置的间隙的TSV。 在TSV上形成相应的焊球以连接到DRAM TSV堆叠中的另一个DRAM芯片。 金属层通过一个相应的焊球连接到至少一个TSV，并且连接到电压源，并且电介质插入在DRAM TSV堆叠中的金属层之间以完成去耦电容器。

公开(公告)号：US08343804B2

公开(公告)日：2013-01-01

申请号：US13364346

申请日：2012-02-02

申请人： Paul W. Coteus ,  Kyu-hyoun Kim

发明人： Paul W. Coteus ,  Kyu-hyoun Kim

IPC分类号： H01L21/00

CPC分类号： H01L24/73 ,  H01L23/481 ,  H01L24/06 ,  H01L24/48 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/10253 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2224/45099 ,  H01L2924/00

摘要： A method and structure are provided for implementing multiple different types of dies for memory stacking. A common wafer is provided with a predefined reticle type. The reticle type includes a plurality of arrays, and a plurality of periphery segments. A plurality of through-silicon-vias (TSVs) is placed at boundaries between array and periphery segments. Multiple different types of dies for memory stacking are obtained based upon selected scribing of the dies from the common wafer.

摘要翻译： 提供了一种用于实现用于存储器堆叠的多种不同类型的管芯的方法和结构。 普通晶片具有预定的掩模版类型。 标线型包括多个阵列和多个外围段。 多个通硅通孔（TSV）被放置在阵列和外围段之间的边界处。 基于从公共晶片选择划线的模具，获得用于存储器堆叠的多种不同类型的管芯。

公开(公告)号：US20120151131A1

公开(公告)日：2012-06-14

申请号：US12963797

申请日：2010-12-09

申请人： Charles A. Kilmer ,  Kyu-hyoun Kim ,  Warren E. Maule ,  Vipin Patel

发明人： Charles A. Kilmer ,  Kyu-hyoun Kim ,  Warren E. Maule ,  Vipin Patel

IPC分类号： G06F12/00 ,  G11C11/406

CPC分类号： G11C11/406 ,  G11C2211/4061 ,  G11C2211/4065

摘要： A memory system with a programmable refresh cycle including a memory device that includes a memory array of memory cells and refresh circuitry that is in communication with the memory array and with a memory controller. The refresh circuitry is configured to receive a refresh command from the memory controller and for refreshing a number of the memory cells in the memory device in response to receiving the refresh command. The number of memory cells refreshed in response to receiving the refresh command is programmable.

摘要翻译： 一种具有可编程刷新周期的存储器系统，包括存储器件，该存储器件包括与存储器阵列和存储器控制器通信的存储器单元的存储器阵列和刷新电路。 刷新电路被配置为响应于接收到刷新命令从存储器控制器接收刷新命令并且用于刷新存储器件中的多个存储器单元。 响应于接收刷新命令刷新的存储器单元的数量是可编程的。