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19 条记录 (耗时 0.021 秒)

    Sigma-delta based phase lock loop
    2.
    发明授权
    Sigma-delta based phase lock loop 有权
    基于Sigma-delta的锁相环

    公开(公告)号：US07535977B2

    公开(公告)日：2009-05-19

    申请号：US11227909

    申请日：2005-09-16

    申请人： Yido Koo ,  Youngho Ahn ,  Eunseok Song ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

    发明人： Yido Koo ,  Youngho Ahn ,  Eunseok Song ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

    IPC分类号： H03D3/18

    CPC分类号： H03L7/0895 ,  H03L7/1976

    摘要： A sigma-delta based phase lock loop device is provided that includes a phase frequency detector (PFD), a charge pump and a voltage controlled oscillator. The PFD to receive a reference signal and a feedback signal and to output signals based on a comparison of the reference signal and the feedback signal. The charge pump to output a charge based on the output signals from the PFD. The charge pump including a first current source to apply a fixed amount of current and a second current source to apply a variable amount of current. The voltage controlled oscillator to output a clock signal based on the received charge from the charge pump.

    摘要翻译： 提供了一种基于Σ-Δ的锁相环装置，其包括相位频率检测器（PFD），电荷泵和压控振荡器。 PFD接收参考信号和反馈信号，并且基于参考信号和反馈信号的比较来输出信号。 电荷泵根据PFD的输出信号输出电荷。 电荷泵包括施加固定电流量的第一电流源和第二电流源以施加可变量的电流。 压控振荡器根据来自电荷泵的接收电荷输出时钟信号。

    System and method for suppressing noise in a phase-locked loop circuit
    3.
    发明授权
    System and method for suppressing noise in a phase-locked loop circuit 有权
    用于抑制锁相环电路中的噪声的系统和方法

    公开(公告)号：US06952125B2

    公开(公告)日：2005-10-04

    申请号：US10689986

    申请日：2003-10-22

    申请人： Youngho Ahn ,  Eunseok Song ,  Yido Koo ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

    发明人： Youngho Ahn ,  Eunseok Song ,  Yido Koo ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

    IPC分类号： H03L7/197 ,  H03L7/06 ,  H03L7/08

    CPC分类号： H03L7/1978

    摘要： A system and method for improving the signal-to-noise ratio of a frequency generator suppresses phase noise and noise generated from mismatches in the internal generator circuits. This is accomplished using a modulation scheme which shifts spurious noise signals outside the loop bandwidth of the generator. When shifted in this manner, the noise signals maybe removed entirely or to any desired degree using, for example, a filter located along the signal path of the generator. In one embodiment, a Sigma-Delta modulator controls the value of a pulse-swallow frequency divider situated along a feedback path of a phase-locked loop to achieve a desired level of noise suppression. In another embodiment, a reference signal input into a phase-locked loop is modulated to effect noise suppression. In another embodiment, the foregoing forms of modulation are combined to accomplish the desired frequency shift. Through these modulation techniques, the signal-to-noise ratio of the frequency generator may be substantially improved while simultaneously achieving faster lock times.

    摘要翻译： 用于提高频率发生器的信噪比的系统和方法抑制由内部发生器电路中的失配产生的相位噪声和噪声。 这是使用将发生器的环路带宽之外的杂散噪声信号移位的调制方案来实现的。 当以这种方式移位时，噪声信号可以使用例如沿着发生器的信号路径定位的滤波器被完全去除或达到任何期望的程度。 在一个实施例中，Σ-Δ调制器控制沿着锁相环路的反馈路径设置的脉冲吞咽分频器的值，以实现期望的噪声抑制水平。 在另一个实施例中，输入到锁相环的参考信号被调制以实现噪声抑制。 在另一个实施例中，组合上述形式的调制以实现期望的频移。 通过这些调制技术，可以显着提高频率发生器的信噪比，同时实现更快的锁定时间。

    Frequency synthesizer using two phase locked loops
    4.
    发明申请
    Frequency synthesizer using two phase locked loops 有权
    频率合成器使用两个锁相环

    公开(公告)号：US20080197891A1

    公开(公告)日：2008-08-21

    申请号：US11902358

    申请日：2007-09-20

    申请人： Joonbae Park ,  Kyeongho Lee ,  Yido Koo ,  Jeong-Woo Lee

    发明人： Joonbae Park ,  Kyeongho Lee ,  Yido Koo ,  Jeong-Woo Lee

    IPC分类号： H03L7/22 ,  H03B21/01

    CPC分类号： H03L7/23 ,  H03L7/183 ,  H03L7/1976

    摘要： The application discloses system and method embodiments related to a frequency synthesizer. Embodiments of a frequency synthesizer can have a low phase noise and a narrow channel spacing. Embodiments of a frequency synthesizer can use two phase locked loops. One embodiment of a frequency synthesizer can include a reference frequency oscillator for outputting a signal having a reference frequency, an integer-N phase locked loop to generate a first output frequency signal based on the reference frequency signal, a fractional-N phase locked loop to generate a second output frequency based on the reference frequency signal and a circuit to generate an output frequency signal by combining the first output frequency and the second output frequency.

    摘要翻译： 本申请公开了与频率合成器相关的系统和方法实施例。 频率合成器的实施例可以具有低相位噪声和窄通道间隔。 频率合成器的实施例可以使用两个锁相环。 频率合成器的一个实施例可以包括：参考频率振荡器，用于输出具有参考频率的信号，整数N个锁相环，以基于参考频率信号产生第一输出频率信号;分数N相锁相环 基于参考频率信号产生第二输出频率，以及通过组合第一输出频率和第二输出频率来产生输出频率信号的电路。

    Sample and hold type fractional-N frequency synthesizer
    5.
    发明授权
    Sample and hold type fractional-N frequency synthesizer 有权
    采样和保持型小数N频率合成器

    公开(公告)号：US06704383B2

    公开(公告)日：2004-03-09

    申请号：US09940808

    申请日：2001-08-29

    申请人： Jeongwoo Lee ,  Yido Koo ,  Kang Yoon Lee ,  Eunseok Song ,  Hyungki Huh ,  Joonbae Park ,  Kyeongho Lee

    发明人： Jeongwoo Lee ,  Yido Koo ,  Kang Yoon Lee ,  Eunseok Song ,  Hyungki Huh ,  Joonbae Park ,  Kyeongho Lee

    IPC分类号： H03D324

    CPC分类号： H03L7/0898 ,  H03L7/087 ,  H03L7/095 ,  H03L7/1976

    摘要： A phase-locked loop (PLL) fractional-N type frequency synthesizer incorporates a sample-and-hold circuit. The synthesizer can reduce circuit size by eliminating a loop filter. Further, the synthesizer can incorporate fractional spur compensation circuitry to compensate charge pump ripple whenever a charge pump operates. The synthesizer or fractional-N type PLL can use a divider and at least two phase detectors coupled to a sample-and-hold circuit. A lock detecting circuit can initially determine a reference voltage for the sample-and-hold circuit. Also, fractional compensation is accomplished dynamically and in a manner that is robust to environmental changes while a control voltage is stably maintained for the voltage controlled oscillator.

    摘要翻译： 锁相环（PLL）小数N型频率合成器包含采样保持电路。 合成器可以通过消除环路滤波器来减小电路尺寸。 此外，合成器可以包括分数支路补偿电路，以便在电荷泵工作时补偿电荷泵波动。 合成器或分数N型PLL可以使用分频器和耦合到采样和保持电路的至少两个相位检测器。 锁定检测电路可以最初确定采样和保持电路的参考电压。 此外，分数补偿是动态地实现的，并且以对于环境变化是稳健的方式实现，同时稳定地维持用于压控振荡器的控制电压。

    Integrated circuit package having inductance loop formed from a bridge interconnect
    9.
    发明申请
    Integrated circuit package having inductance loop formed from a bridge interconnect 有权
    集成电路封装，其具有由桥互连形成的电感环路

    公开(公告)号：US20050045988A1

    公开(公告)日：2005-03-03

    申请号：US10927152

    申请日：2004-08-27

    申请人： Yido Koo ,  Hyungki Huh ,  Kang Yoon Lee ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

    发明人： Yido Koo ,  Hyungki Huh ,  Kang Yoon Lee ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

    IPC分类号： H01L20060101 ,  H01L23/64 ,  H01L29/00 ,  H03B5/12

    CPC分类号： H01L23/642 ,  H01L23/645 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1265 ,  H01L2224/45099 ,  H01L2224/05599

    摘要： An integrated circuit package includes an inductance loop formed from a connection of lead wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from a first wire which connects a first bonding pad on the integrated circuit chip to a first I/O pin of the package and a second wire which connects a second bonding pad on the chip to a second I/O pin of the package. To complete the inductor loop, the first and second I/O pins are connected by a conductive bridge between the pins. The bridge may be formed by making the I/O pins have a unitary construction. In another embodiment, the bridge is formed by a metallization layer located either on the surface of the package substrate or within this substrate. The I/O pins are preferably ones which are adjacent one another; however, the loop may be formed from non-adjacent connections of I/O pins based, for example, on loop-length requirements, space considerations, and/or other design or functional factors. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization. Also, the integrated circuit may be implemented in any one of a variety of systems, at least one parameter of which is controlled by the length of the inductor loop of the package.

    摘要翻译： 集成电路封装包括由引线和一个或多个输入/输出（I / O）封装引脚的连接形成的电感回路。 在一个实施例中，电感回路由将集成电路芯片上的第一接合焊盘连接到封装的第一I / O引脚的第一引线和将芯片上的第二接合焊盘连接到第二引线的第二引线形成 封装的I / O引脚。 为了完成电感环路，第一和第二I / O引脚通过引脚之间的导电桥连接。 可以通过使I / O引脚具有单一结构来形成桥。 在另一个实施例中，桥由位于封装衬底的表面上或在该衬底内的金属化层形成。 I / O引脚优选为彼此相邻的引脚; 然而，环路可以基于例如环路长度要求，空间考虑和/或其他设计或功能因素的I / O引脚的不相邻连接形成。 通过在集成电路封装的极限内形成电感器回路，实现了空间要求的显着降低，这反过来促进了小型化。 此外，集成电路可以在各种系统中的任何一个中实现，其中的至少一个参数由封装的电感器环的长度来控制。