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11 条记录 (耗时 0.022 秒)

    Sigma-delta based phase lock loop
    2.
    发明授权
    Sigma-delta based phase lock loop 有权
    基于Sigma-delta的锁相环

    公开(公告)号：US07535977B2

    公开(公告)日：2009-05-19

    申请号：US11227909

    申请日：2005-09-16

    申请人： Yido Koo ,  Youngho Ahn ,  Eunseok Song ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

    发明人： Yido Koo ,  Youngho Ahn ,  Eunseok Song ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

    IPC分类号： H03D3/18

    CPC分类号： H03L7/0895 ,  H03L7/1976

    摘要： A sigma-delta based phase lock loop device is provided that includes a phase frequency detector (PFD), a charge pump and a voltage controlled oscillator. The PFD to receive a reference signal and a feedback signal and to output signals based on a comparison of the reference signal and the feedback signal. The charge pump to output a charge based on the output signals from the PFD. The charge pump including a first current source to apply a fixed amount of current and a second current source to apply a variable amount of current. The voltage controlled oscillator to output a clock signal based on the received charge from the charge pump.

    摘要翻译： 提供了一种基于Σ-Δ的锁相环装置，其包括相位频率检测器（PFD），电荷泵和压控振荡器。 PFD接收参考信号和反馈信号，并且基于参考信号和反馈信号的比较来输出信号。 电荷泵根据PFD的输出信号输出电荷。 电荷泵包括施加固定电流量的第一电流源和第二电流源以施加可变量的电流。 压控振荡器根据来自电荷泵的接收电荷输出时钟信号。

    System and method for suppressing noise in a phase-locked loop circuit
    3.
    发明授权
    System and method for suppressing noise in a phase-locked loop circuit 有权
    用于抑制锁相环电路中的噪声的系统和方法

    公开(公告)号：US06952125B2

    公开(公告)日：2005-10-04

    申请号：US10689986

    申请日：2003-10-22

    申请人： Youngho Ahn ,  Eunseok Song ,  Yido Koo ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

    发明人： Youngho Ahn ,  Eunseok Song ,  Yido Koo ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

    IPC分类号： H03L7/197 ,  H03L7/06 ,  H03L7/08

    CPC分类号： H03L7/1978

    摘要： A system and method for improving the signal-to-noise ratio of a frequency generator suppresses phase noise and noise generated from mismatches in the internal generator circuits. This is accomplished using a modulation scheme which shifts spurious noise signals outside the loop bandwidth of the generator. When shifted in this manner, the noise signals maybe removed entirely or to any desired degree using, for example, a filter located along the signal path of the generator. In one embodiment, a Sigma-Delta modulator controls the value of a pulse-swallow frequency divider situated along a feedback path of a phase-locked loop to achieve a desired level of noise suppression. In another embodiment, a reference signal input into a phase-locked loop is modulated to effect noise suppression. In another embodiment, the foregoing forms of modulation are combined to accomplish the desired frequency shift. Through these modulation techniques, the signal-to-noise ratio of the frequency generator may be substantially improved while simultaneously achieving faster lock times.

    摘要翻译： 用于提高频率发生器的信噪比的系统和方法抑制由内部发生器电路中的失配产生的相位噪声和噪声。 这是使用将发生器的环路带宽之外的杂散噪声信号移位的调制方案来实现的。 当以这种方式移位时，噪声信号可以使用例如沿着发生器的信号路径定位的滤波器被完全去除或达到任何期望的程度。 在一个实施例中，Σ-Δ调制器控制沿着锁相环路的反馈路径设置的脉冲吞咽分频器的值，以实现期望的噪声抑制水平。 在另一个实施例中，输入到锁相环的参考信号被调制以实现噪声抑制。 在另一个实施例中，组合上述形式的调制以实现期望的频移。 通过这些调制技术，可以显着提高频率发生器的信噪比，同时实现更快的锁定时间。

    Sample and hold type fractional-N frequency synthesizer
    4.
    发明授权
    Sample and hold type fractional-N frequency synthesizer 有权
    采样和保持型小数N频率合成器

    公开(公告)号：US06704383B2

    公开(公告)日：2004-03-09

    申请号：US09940808

    申请日：2001-08-29

    申请人： Jeongwoo Lee ,  Yido Koo ,  Kang Yoon Lee ,  Eunseok Song ,  Hyungki Huh ,  Joonbae Park ,  Kyeongho Lee

    发明人： Jeongwoo Lee ,  Yido Koo ,  Kang Yoon Lee ,  Eunseok Song ,  Hyungki Huh ,  Joonbae Park ,  Kyeongho Lee

    IPC分类号： H03D324

    CPC分类号： H03L7/0898 ,  H03L7/087 ,  H03L7/095 ,  H03L7/1976

    摘要： A phase-locked loop (PLL) fractional-N type frequency synthesizer incorporates a sample-and-hold circuit. The synthesizer can reduce circuit size by eliminating a loop filter. Further, the synthesizer can incorporate fractional spur compensation circuitry to compensate charge pump ripple whenever a charge pump operates. The synthesizer or fractional-N type PLL can use a divider and at least two phase detectors coupled to a sample-and-hold circuit. A lock detecting circuit can initially determine a reference voltage for the sample-and-hold circuit. Also, fractional compensation is accomplished dynamically and in a manner that is robust to environmental changes while a control voltage is stably maintained for the voltage controlled oscillator.

    摘要翻译： 锁相环（PLL）小数N型频率合成器包含采样保持电路。 合成器可以通过消除环路滤波器来减小电路尺寸。 此外，合成器可以包括分数支路补偿电路，以便在电荷泵工作时补偿电荷泵波动。 合成器或分数N型PLL可以使用分频器和耦合到采样和保持电路的至少两个相位检测器。 锁定检测电路可以最初确定采样和保持电路的参考电压。 此外，分数补偿是动态地实现的，并且以对于环境变化是稳健的方式实现，同时稳定地维持用于压控振荡器的控制电压。

    RF front end with reduced carrier leakage
    6.
    发明授权
    RF front end with reduced carrier leakage 有权
    射频前端具有减少的载波泄漏

    公开(公告)号：US06850748B2

    公开(公告)日：2005-02-01

    申请号：US10207986

    申请日：2002-07-31

    申请人： Eunseok Song ,  Seung-Wook Lee ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

    发明人： Eunseok Song ,  Seung-Wook Lee ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

    IPC分类号： H04B1/28 ,  H04B1/52 ,  H04B1/00

    CPC分类号： H04B1/28 ,  H04B1/525

    摘要： A method and apparatus that provide a frequency conversion in a radio frequency front-end are disclosed, including a frequency divider that divides an input signal frequency by a predetermined value to produce an output signal frequency; and a frequency mixer that mixes the output signal frequency with a carrier signal frequency to produce a converted signal frequency, which is substantially equal to a difference between the output signal frequency and the carrier signal frequency. The predetermined value and the input signal frequency are selected such that the carrier signal frequency is not substantially equivalent to an integer multiple of the output signal frequency. The method and apparatus can be used in a wireless communication receiver including wireless communication systems and wireless LAN systems.

    摘要翻译： 公开了一种在射频前端提供频率转换的方法和装置，包括将输入信号频率除以预定值以产生输出信号频率的分频器; 以及混频器，其将输出信号频率与载波信号频率进行混合，以产生基本上等于输出信号频率和载波信号频率之差的转换信号频率。 选择预定值和输入信号频率使得载波信号频率基本上不等于输出信号频率的整数倍。 该方法和装置可用于包括无线通信系统和无线LAN系统的无线通信接收机。

    Communication transmitter using offset phase-locked-loop
    7.
    发明授权
    Communication transmitter using offset phase-locked-loop 失效
    通信发射机使用偏移锁相环

    公开(公告)号：US06963620B2

    公开(公告)日：2005-11-08

    申请号：US10284342

    申请日：2002-10-31

    申请人： Kang-Yoon Lee ,  Eunseok Song ,  Jeong Woo Lee ,  Joonbae Park ,  Kyeongho Lee

    发明人： Kang-Yoon Lee ,  Eunseok Song ,  Jeong Woo Lee ,  Joonbae Park ,  Kyeongho Lee

    IPC分类号： H03C3/09 ,  H04L27/04 ,  H03D3/24 ,  H04L27/12 ,  H04L27/20

    CPC分类号： H03C3/0966 ,  H03C3/0933

    摘要： A translational-loop transmitter generates RF signals using at most one phase-locked-loop (PLL) circuit. In one embodiment, a single PLL generates two local oscillation signals. The first oscillation signal is mixed with a baseband signal to generate an intermediate frequency signal. The second oscillation signal is input into the translational loop to adjust a voltage-controlled oscillator to the desired carrier frequency. In order to perform this type of modulation, the frequencies of the local oscillation signals are set so that they are harmonically related to one another relative to the carrier frequency. Other embodiments generate only one oscillation signal. Under these conditions, the intermediate frequency signal is generated using the oscillation signal, and a frequency divider in the translational loop is used to generate a control signal for adjusting the voltage-controlled oscillator to the carrier frequency. In still other embodiments, a transmitter signal is generated without using any phase-locked-loop circuits. This is accomplished by generating an intermediate frequency signal using a crystal oscillator, and then using a frequency divider in a feedback loop to generate a control signal for adjusting the voltage-controlled oscillator to the carrier frequency. By minimizing the number of phase-locked-loop circuits in the transmitter, the size, cost, and power requirements of mobile handsets may be significantly reduced.

    摘要翻译： 平移环路发射器使用至多一个锁相环（PLL）电路产生RF信号。 在一个实施例中，单个PLL产生两个本地振荡信号。 第一振荡信号与基带信号混合以产生中频信号。 第二振荡信号被输入到平移回路中，以将压控振荡器调整到期望的载波频率。 为了执行这种类型的调制，本地振荡信号的频率被设置为使得它们相对于载波频率彼此谐波相关。 其他实施例仅产生一个振荡信号。 在这些条件下，使用振荡信号产生中频信号，并且使用平移环路中的分频器产生用于将压控振荡器调节到载波频率的控制信号。 在其他实施例中，产生发射机信号而不使用任何锁相环电路。 这是通过使用晶体振荡器产生中频信号，然后在反馈环路中使用分频器来产生用于将压控振荡器调节到载波频率的控制信号来实现的。 通过最小化发射机中的锁相环电路的数量，移动手机的尺寸，成本和功率要求可能会大大降低。

    Low noise amplifier having improved linearity
    8.
    发明申请
    Low noise amplifier having improved linearity 有权
    低噪声放大器具有改善的线性度

    公开(公告)号：US20080252377A1

    公开(公告)日：2008-10-16

    申请号：US11976911

    申请日：2007-10-29

    申请人： Seung-Wook Lee ,  Deok Hee Lee ,  Eunseok Song ,  Joonbae Park ,  Kyeongho Lee

    发明人： Seung-Wook Lee ,  Deok Hee Lee ,  Eunseok Song ,  Joonbae Park ,  Kyeongho Lee

    IPC分类号： H03G3/30 ,  H04B1/16

    CPC分类号： H03F1/223 ,  H03F3/193 ,  H03F2200/372

    摘要： Embodiments of the present general inventive concept include a low noise amplifier and method with an improved linearity while reducing a noise disadvantage (e.g., increase). One embodiment of a low noise amplifier can include a first transistor to receive an input signal at a control terminal thereof, a second transistor having a first terminal coupled to a second terminal of the first transistor, an envelope detector to output a control signal corresponding to a characteristic of the input signal and an envelope amplifier to amplify the control signal to be applied to a control terminal of the second transistor.

    摘要翻译： 本发明总体构思的实施例包括具有改善的线性度的低噪声放大器和方法，同时降低噪声不利（例如增加）。 低噪声放大器的一个实施例可以包括在其控制端接收输入信号的第一晶体管，具有耦合到第一晶体管的第二端的第一端的第二晶体管，用于输出对应于 输入信号的特性和包络放大器，放大要施加到第二晶体管的控制端的控制信号。

    Low noise amplifier having improved linearity
    9.
    发明授权
    Low noise amplifier having improved linearity 有权
    低噪声放大器具有改善的线性度

    公开(公告)号：US07812672B2

    公开(公告)日：2010-10-12

    申请号：US11976911

    申请日：2007-10-29

    申请人： Seung-Wook Lee ,  Deok Hee Lee ,  Eunseok Song ,  Joonbae Park ,  Kyeongho Lee

    发明人： Seung-Wook Lee ,  Deok Hee Lee ,  Eunseok Song ,  Joonbae Park ,  Kyeongho Lee

    IPC分类号： H03F3/30

    CPC分类号： H03F1/223 ,  H03F3/193 ,  H03F2200/372

    摘要： Embodiments of the present general inventive concept include a low noise amplifier and method with an improved linearity while reducing a noise disadvantage (e.g., increase). One embodiment of a low noise amplifier can include a first transistor to receive an input signal at a control terminal thereof, a second transistor having a first terminal coupled to a second terminal of the first transistor, an envelope detector to output a control signal corresponding to a characteristic of the input signal and an envelope amplifier to amplify the control signal to be applied to a control terminal of the second transistor.

    摘要翻译： 本发明总体构思的实施例包括具有改善的线性度的低噪声放大器和方法，同时降低噪声不利（例如增加）。 低噪声放大器的一个实施例可以包括在其控制端接收输入信号的第一晶体管，具有耦合到第一晶体管的第二端的第一端的第二晶体管，用于输出对应于 输入信号的特性和包络放大器，放大要施加到第二晶体管的控制端的控制信号。