公开(公告)号：US08281160B1

公开(公告)日：2012-10-02

申请号：US12400604

申请日：2009-03-09

申请人： Yu Bai ,  Priya Vaidya ,  Premanand Sakarda

发明人： Yu Bai ,  Priya Vaidya ,  Premanand Sakarda

IPC分类号： G06F1/00

CPC分类号： G06F1/3228 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： Methods, apparatus, and computer program products for implementing power management within Systems on Chips (SOCs). The method includes selecting an operating frequency for a chip from an operating frequency point set that provides a desired overall power dissipation value.

摘要翻译： 用于在芯片系统（SOC）中实现电源管理的方法，设备和计算机程序产品。 该方法包括从提供期望的总功耗值的工作频点集中选择芯片的工作频率。

公开(公告)号：US20060123253A1

公开(公告)日：2006-06-08

申请号：US11007098

申请日：2004-12-07

申请人： Bryan Morgan ,  Premanand Sakarda ,  Priya Vaidya ,  Yi Ge ,  Zhou Gao ,  Swee-chin Pang ,  Manoj Thadani ,  Canhui Yuan

发明人： Bryan Morgan ,  Premanand Sakarda ,  Priya Vaidya ,  Yi Ge ,  Zhou Gao ,  Swee-chin Pang ,  Manoj Thadani ,  Canhui Yuan

IPC分类号： G06F1/26

CPC分类号： G06F1/3228 ,  G06F1/324 ,  Y02D10/126

摘要： A processing system may include a performance monitoring unit (PMU), a machine accessible medium, and a processor responsive to the PMU and the machine accessible medium. Instructions encoded in the machine accessible medium, when executed by the processor, may determine whether performance details for the processing system should be collected, based at least in part on a predetermined monitoring policy for the processing system. The instructions may generate performance data for the processing system, based at least in part on data obtained from the PMU. The instructions may determine whether the processing system should be reconfigured, based at least in part on the performance data and a power policy profile for the processing system. The instructions may automatically adjust power consumption of the processing system by using the PMU to reconfigure the processing system. Other embodiments are described and claimed.

摘要翻译： 处理系统可以包括性能监视单元（PMU），机器可访问介质和响应于PMU和机器可访问介质的处理器。 在机器可访问介质中编码的指令在由处理器执行时可以至少部分地基于用于处理系统的预定监视策略来确定是否应该收集处理系统的性能细节。 该指令可以至少部分地基于从PMU获得的数据来生成处理系统的性能数据。 所述指令可以至少部分地基于所述处理系统的性能数据和功率策略简档来确定所述处理系统是否应被重新配置。 该指令可以通过使用PMU重新配置处理系统来自动调整处理系统的功耗。 描述和要求保护其他实施例。

公开(公告)号：US09442758B1

公开(公告)日：2016-09-13

申请号：US12356761

申请日：2009-01-21

申请人： Premanand Sakarda ,  Scott B. Peirce ,  Jia Bao ,  Marlon Moncrieffe ,  Priya Vaidya ,  Michael D Rosenzweig ,  Minda Zhang ,  Palanisamy Mohanraj

发明人： Premanand Sakarda ,  Scott B. Peirce ,  Jia Bao ,  Marlon Moncrieffe ,  Priya Vaidya ,  Michael D Rosenzweig ,  Minda Zhang ,  Palanisamy Mohanraj

IPC分类号： G06F9/40 ,  G06F9/48 ,  G06F9/50

CPC分类号： G06F9/4856 ,  B60K7/0007 ,  B60K17/043 ,  B60K17/30 ,  B60K2007/0046 ,  B60K2007/0061 ,  B60L2220/46 ,  G06F9/5088

摘要： Dynamic processor core switching is described. In embodiments, a multi-core processor system can include a first processor core that executes computer instructions at a first processing rate, and can include at least a second processor core that executes the computer instructions at a second processing rate, where the second processing rate is different than the first processing rate. A core profiler can generate system profile data that is evaluated to determine when a core-switch manager initiates switching execution of the computer instructions from the first processor core to the second processor core while the computer instructions are being executed.

摘要翻译： 描述了动态处理器核心交换。 在实施例中，多核处理器系统可以包括以第一处理速率执行计算机指令的第一处理器核心，并且可以包括以第二处理速率执行计算机指令的至少第二处理器核心， 与第一个处理速度不同。 核心分析器可以生成被评估的系统简档数据，以便在计算机指令被执行时核心交换管理器何时启动计算机指令从第一处理器核心切换到第二处理器核心的执行。

公开(公告)号：US20060123252A1

公开(公告)日：2006-06-08

申请号：US11006917

申请日：2004-12-07

申请人： Priya Vaidya ,  Premanand Sakarda ,  Bryan Morgan ,  Yi Ge

发明人： Priya Vaidya ,  Premanand Sakarda ,  Bryan Morgan ,  Yi Ge

IPC分类号： G06F1/30

CPC分类号： G06F1/3228 ,  G06F1/324 ,  Y02D10/126

摘要： A disclosed method involves initializing a performance profiler of a processing system. The performance profiler may include performance profile parameters for a power management policy for the processing system. The method also involves retrieving performance metrics for the processing system from a performance monitoring unit (PMU) of the processing system, in response to a determination that performance details should be collected. A current performance state of the processing system may be determined, based at least in part on the performance profile parameters and the performance metrics from the PMU. The current performance state may then be communicated to a policy manager of the processing system. Other embodiments are disclosed and claimed.

摘要翻译： 所公开的方法涉及初始化处理系统的性能分析器。 性能分析器可以包括用于处理系统的电源管理策略的性能简档参数。 该方法还涉及从处理系统的性能监视单元（PMU）检索处理系统的性能指标，以响应于应该收集性能细节的确定。 可以至少部分地基于来自PMU的性能简档参数和性能度量来确定处理系统的当前性能状态。 可以将当前的性能状态传送给处理系统的策略管理器。 公开和要求保护其他实施例。

公开(公告)号：US08689021B1

公开(公告)日：2014-04-01

申请号：US13216928

申请日：2011-08-24

申请人： Yu Bai ,  Marlon Moncrieffe ,  Bryan Morgan ,  Scott B. Peirce ,  Premanand Sakarda

发明人： Yu Bai ,  Marlon Moncrieffe ,  Bryan Morgan ,  Scott B. Peirce ,  Premanand Sakarda

IPC分类号： G06F1/00

CPC分类号： G06F1/28 ,  G06F1/26 ,  G06F1/329 ,  G06F9/50 ,  G06F9/5094 ,  Y02D10/22 ,  Y02D10/24

摘要： Some of the embodiments of the present disclosure provide a method comprising generating a plurality of power profiles for a corresponding plurality of processing cores, wherein each power profile of the plurality of power profiles includes power consumptions of a corresponding processing core under various operating conditions; generating a plurality of candidate configurations, wherein each candidate configuration comprises corresponding candidate operating conditions for the plurality of processing cores; and based at least in part on the plurality of power profiles, selecting a first candidate configuration of the plurality of candidate configurations for managing the plurality of processing cores. Other embodiments are also described and claimed.

摘要翻译： 本公开的一些实施例提供了一种方法，包括为相应的多个处理核生成多个功率曲线，其中多个功率曲线的每个功率曲线包括在各种操作条件下对应的处理核的功耗; 生成多个候选配置，其中每个候选配置包括用于所述多个处理核的对应候选操作条件; 并且至少部分地基于所述多个功率简档，选择用于管理所述多个处理核心的所述多个候选配置的第一候选配置。 还描述和要求保护其他实施例。

公开(公告)号：US09069553B2

公开(公告)日：2015-06-30

申请号：US13604407

申请日：2012-09-05

申请人： Ofer Zaarur ,  Premanand Sakarda

发明人： Ofer Zaarur ,  Premanand Sakarda

IPC分类号： G06F9/46 ,  G06F1/32 ,  G06F9/48 ,  G06F9/50 ,  G06F9/44

CPC分类号： G06F1/3287 ,  G06F1/329 ,  G06F1/3293 ,  G06F9/44 ,  G06F9/4856 ,  G06F9/5094 ,  Y02D10/122 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/24 ,  Y02D10/32

摘要： The present disclosure describes techniques for switching tasks between heterogeneous cores. In some aspects it is determined that a task being executed by a first core of a processor can be executed by a second core of a processor, the second core having an instruction set that is different from that of the first core, and execution of the task is switched from the first core to the second core effective to decrease an amount of energy consumed by the processor.

摘要翻译： 本公开描述了用于在异构核之间切换任务的技术。 在一些方面，确定由处理器的第一核执行的任务可以由处理器的第二核执行，第二核具有与第一核不同的指令集，并且执行 任务从第一核心切换到第二核心有效地减少处理器消耗的能量的量。

公开(公告)号：US08402293B2

公开(公告)日：2013-03-19

申请号：US13171157

申请日：2011-06-28

申请人： Bryan C. Morgan ,  Priya N. Vaidya ,  Premanand Sakarda ,  Marlon A. Moncrieffe

发明人： Bryan C. Morgan ,  Priya N. Vaidya ,  Premanand Sakarda ,  Marlon A. Moncrieffe

IPC分类号： G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/3246 ,  G06F1/3275 ,  Y02D10/13 ,  Y02D10/14

摘要： In one embodiment, an electronic apparatus comprises at least one processor and a computer readable medium coupled to the processor and comprising logic instructions encoded in the computer readable medium, wherein the instructions, when executed in a processing system, cause the processing system to perform operations comprising initializing a direct memory access profiler in an electronic system, wherein the direct memory access is coupled to a policy manager in the electronic system, measuring at least one memory consumption characteristic of the electronic system, communicating the at least one memory consumption characteristic to a policy manager of the electronic system, and using the at least one memory consumption characteristic to adjust a power state of the electronic system.

公开(公告)号：US20090172432A1

公开(公告)日：2009-07-02

申请号：US12006064

申请日：2007-12-28

申请人： Bryan C. Morgan ,  Priya N. Vaidya ,  Premanand Sakarda ,  Marlon A. Moncrieffe

发明人： Bryan C. Morgan ,  Priya N. Vaidya ,  Premanand Sakarda ,  Marlon A. Moncrieffe

IPC分类号： G06F1/26

CPC分类号： G06F1/3203 ,  G06F1/3246 ,  G06F1/3275 ,  Y02D10/13 ,  Y02D10/14

摘要： In one embodiment, an electronic apparatus comprises at least one processor and a computer readable medium coupled to the processor and comprising logic instructions encoded in the computer readable medium, wherein the instructions, when executed in a processing system, cause the processing system to perform operations comprising initializing a direct memory access profiler in an electronic system, wherein the direct memory access is coupled to a policy manager in the electronic system, measuring at least one memory consumption characteristic of the electronic system, communicating the at least one memory consumption characteristic to a policy manager of the electronic system, and using the at least one memory consumption characteristic to adjust a power state of the electronic system.

摘要翻译： 在一个实施例中，电子设备包括耦合到处理器的至少一个处理器和计算机可读介质，并且包括编码在计算机可读介质中的逻辑指令，其中当在处理系统中执行时，指令使处理系统执行操作 包括在电子系统中初始化直接存储器访问分析器，其中所述直接存储器访问耦合到所述电子系统中的策略管理器，测量所述电子系统的至少一个存储器消耗特性，将所述至少一个存储器消耗特性传达到 电子系统的策略管理器，并且使用至少一个存储器消耗特性来调整电子系统的功率状态。

公开(公告)号：US09158355B2

公开(公告)日：2015-10-13

申请号：US12215760

申请日：2008-06-30

申请人： Sehat Sutardja ,  Hong-Yi Chen ,  Premanand Sakarda ,  Mark N. Fullerton ,  Jay Heeb

发明人： Sehat Sutardja ,  Hong-Yi Chen ,  Premanand Sakarda ,  Mark N. Fullerton ,  Jay Heeb

IPC分类号： G06F15/76 ,  G06F1/32 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48

CPC分类号： G06F1/3293 ,  G06F1/3203 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/38 ,  G06F9/3885 ,  G06F9/461 ,  G06F9/4856 ,  G06F9/4893 ,  Y02D10/122 ,  Y02D10/171 ,  Y02D10/24 ,  Y02D10/32 ,  Y02D50/20

摘要： A core switching system includes a mode switching module that receives a switch signal to switch operation between a first mode and a second mode. During the first mode, instructions associated with applications are executed by a first asymmetric core, and a second asymmetric core is inactive. During the second mode, the instructions are executed by the second asymmetric core, and the first asymmetric core is inactive. A core activation module stops processing of the applications by the first asymmetric core after interrupts are disabled. A state transfer module transfers a state of the first asymmetric core to the second asymmetric core. The core activation module allows the second asymmetric core to resume execution of the instructions and the interrupts are enabled.

摘要翻译： 核心交换系统包括模式切换模块，其接收切换信号以在第一模式和第二模式之间切换操作。 在第一模式期间，与应用相关联的指令由第一不对称核执行，而第二非对称核是不活动的。 在第二模式期间，指令由第二非对称核执行，第一非对称核是不活动的。 核心激活模块在禁止中断之后停止第一个非对称核心处理应用程序。 状态转移模块将第一不对称核的状态转移到第二不对称核。 核心激活模块允许第二非对称核继续执行指令，中断被使能。

公开(公告)号：US20140101411A1

公开(公告)日：2014-04-10

申请号：US13645081

申请日：2012-10-04

申请人： Premanand Sakarda

发明人： Premanand Sakarda

IPC分类号： G06F9/30 ,  G06F15/76

CPC分类号： G06F9/4893 ,  G06F1/329 ,  G06F9/3885 ,  G06F2209/5019 ,  Y02D10/24

摘要： In one embodiment, a policy manager may receive operating system scheduling information, performance prediction information for at least one future quantum, and current processor utilization information, and determine a performance prediction for a future quantum and whether to cause a switch between asymmetric cores of a multicore processor based at least in part on this received information. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，策略管理器可以接收操作系统调度信息，用于至少一个未来量子的性能预测信息和当前处理器利用信息，并且确定未来量子的性能预测以及是否导致在 至少部分地基于该接收到的信息的多核处理器。 描述和要求保护其他实施例。