公开(公告)号：USRE34025E

公开(公告)日：1992-08-11

申请号：US620536

申请日：1990-11-28

申请人： Yosuke Takagi ,  Yu Ohata ,  Koichi Kitahara ,  Tsuyoshi Kuramoto

发明人： Yosuke Takagi ,  Yu Ohata ,  Koichi Kitahara ,  Tsuyoshi Kuramoto

IPC分类号： H01L21/761 ,  H01L21/8249 ,  H01L27/06

CPC分类号： H01L21/8249 ,  H01L21/761 ,  H01L27/0623

摘要： A semiconductor device is provided which has a power insulated-gate MOS field effect transistor and a control semiconductor element formed in a common semiconductor substrate. A first area corresponding to a drain region of low resistance in the power MOS field effect transistor is different in resistivity than a second area corresponding to the control semiconductor element. The electrical characteristics of each element integrated in the devices is substantially equal to the same element in discrete form.

公开(公告)号：US4879584A

公开(公告)日：1989-11-07

申请号：US154275

申请日：1988-02-10

申请人： Yosuke Takagi ,  Yu Ohata ,  Koichi Kitahara ,  Tsuyoshi Kuramoto

发明人： Yosuke Takagi ,  Yu Ohata ,  Koichi Kitahara ,  Tsuyoshi Kuramoto

IPC分类号： H01L21/76 ,  H01L21/8238 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L21/8249 ,  H01L27/0623 ,  H01L27/088

摘要： A semiconductor device is provided which has a power insulated-gate MOS field effect transistor and a control semiconductor element formed in a common semiconductor substrate. A first area corresponding to a drain region of low resistance in the power MOS field effect transistor is different in resistivity than a second area corresponding to the control semiconductor element. The electrical characteristics of each element integrated in the devices is substantially equal to the same element in discrete form.

公开(公告)号：US5493148A

公开(公告)日：1996-02-20

申请号：US956466

申请日：1992-10-02

申请人： Yu Ohata ,  Koichi Kitahara ,  Yosuke Takagi

发明人： Yu Ohata ,  Koichi Kitahara ,  Yosuke Takagi

IPC分类号： H01L27/04 ,  H01C17/22 ,  H01L21/82 ,  H01L21/822 ,  H01L23/525 ,  H01L29/00

CPC分类号： H01C17/22 ,  H01L23/5256 ,  H01L2924/0002

摘要： A semiconductor device includes a resistor network having a plurality of trimming polysilicon resistors. The polysilicon resistors have the same width and different lengths and can be selectively fused according to the value of current which is caused to flow therein. The resultant resistance of the resistor network is changed by selectively fusing the polysilicon resistors. The output characteristic of the semiconductor device can be adjusted by changing the resultant resistance.

摘要翻译： 半导体器件包括具有多个微调多晶硅电阻器的电阻网络。 多晶硅电阻器具有相同的宽度和不同的长度，并且可以根据流过其中的电流的值选择性地熔化。 通过选择性地熔化多晶硅电阻来改变电阻网络的合成电阻。 可以通过改变所得到的电阻来调节半导体器件的输出特性。

公开(公告)号：US5418383A

公开(公告)日：1995-05-23

申请号：US143060

申请日：1993-10-29

申请人： Yosuke Takagi ,  Yu Ohata ,  Koichi Kitahara

发明人： Yosuke Takagi ,  Yu Ohata ,  Koichi Kitahara

IPC分类号： H01L21/66 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/04 ,  H01L27/088 ,  H01L23/58 ,  H01L23/62 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L27/0255 ,  H01L2924/0002

摘要： At least one power output element made of an insulated gate semiconductor element, a surge protection element for an input electrode of the power output element, and a circuit element block for controlling the power output element, are formed on the same semiconductor substrate. A predetermined electrode of the power output element and one end of the surge protection element are connected to each other. In this state, first, second, and third electrode wiring layers are connected to an output terminal of the circuit element block, the other end of the surge protection element, and the input electrode of the power output element, respectively, and the first to third electrode wiring layers are formed separately from one another. In order to connect the first to third electrode wiring layers to each other, a fourth electrode wiring layer is formed thereon. Thus, a characteristic of the power output element is previously evaluated before the fourth electrode wiring layer is formed, using at least the third electrode wiring layer.

摘要翻译： 在同一半导体基板上形成由绝缘栅极半导体元件构成的至少一个功率输出元件，用于输出功率输出元件的输入电极的浪涌保护元件和用于控制功率输出元件的电路元件块。 功率输出元件的预定电极和浪涌保护元件的一端彼此连接。 在这种状态下，第一，第二和第三电极布线层分别连接到电路元件块的输出端子，浪涌保护元件的另一端和功率输出元件的输入电极，第一至第 第三电极布线层彼此分开地形成。 为了将第一至第三电极布线层彼此连接，在其上形成第四电极布线层。 因此，在形成第四电极布线层之前，至少使用第三电极布线层，预先评估功率输出元件的特性。

公开(公告)号：US4948748A

公开(公告)日：1990-08-14

申请号：US396792

申请日：1989-08-21

申请人： Koichi Kitahara ,  Yu Ohata ,  Tsuyoshi Kuramoto

发明人： Koichi Kitahara ,  Yu Ohata ,  Tsuyoshi Kuramoto

IPC分类号： H01L21/02 ,  H01L21/20 ,  H01L21/762 ,  H01L27/088 ,  H01L27/12

CPC分类号： H01L21/76294 ,  H01L21/2007 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76278 ,  H01L21/76286 ,  H01L27/088 ,  H01L2924/0002 ,  Y10S148/012 ,  Y10S148/135

摘要： A substrate structure for a composite semiconductor device comprises first and second semiconductor substrates whose major surfaces are bonded to each other with an insulating layer interposed therebetween. In this substrate structure, an epitaxial layer is grown from part of the second semiconductor substrate, forming one element area, and another element area is formed in the first semiconductor substrate area and isolated from the epitaxial layer.

摘要翻译： 用于复合半导体器件的衬底结构包括其主表面彼此接合的第一和第二半导体衬底，其间插入有绝缘层。 在该衬底结构中，从第二半导体衬底的一部分生长外延层，形成一个元件区域，并且在第一半导体衬底区域中形成另一个元件区域并与外延层隔离。

公开(公告)号：US4837186A

公开(公告)日：1989-06-06

申请号：US84209

申请日：1987-08-12

申请人： Yu Ohata ,  Tsuyoshi Kuramoto ,  Masaru Shimbo

发明人： Yu Ohata ,  Tsuyoshi Kuramoto ,  Masaru Shimbo

IPC分类号： H01L21/18 ,  H01L21/762 ,  H01L27/06 ,  H01L27/088

CPC分类号： H01L21/187 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76283 ,  H01L21/76286 ,  H01L27/0623 ,  H01L27/088 ,  Y10S148/012

摘要： A silicon semiconductor substrate includes an insulating layer embedded therein. The silicon semiconductor substrate comprises a first silicon plate, an insulating layer embedded in the first silicon plate so that the surfaces of the silicon plate and the insulating layer are in a mirror surface, and a second silicon plate united with the first silicon plate and the insulating layer at the mirror surface of the first silicon plate and the insulating layer. The insulating layer is used for forming an isolated region in the second silicon plate.

摘要翻译： 硅半导体衬底包括嵌入其中的绝缘层。 硅半导体衬底包括第一硅板，嵌入在第一硅板中的绝缘层，使得硅板和绝缘层的表面在镜面中，并且第二硅板与第一硅板和 第一硅板的镜面上的绝缘层和绝缘层。 绝缘层用于在第二硅板中形成隔离区域。

公开(公告)号：US5065212A

公开(公告)日：1991-11-12

申请号：US436004

申请日：1989-11-13

申请人： Yu Ohata ,  Tsuyoshi Kuramoto

发明人： Yu Ohata ,  Tsuyoshi Kuramoto

IPC分类号： H01L27/088 ,  H01L21/74 ,  H01L21/76 ,  H01L21/761 ,  H01L21/8234 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/739 ,  H01L29/78

CPC分类号： H01L21/8249 ,  H01L21/74 ,  H01L21/743 ,  H01L21/761 ,  H01L27/0623 ,  H01L29/7395

摘要： There is a semiconductor device in which an n-type layer formed on a p.sup.+ -type substrate is divided into first and second device forming regions by an isolation region and drive circuit devices and an output circuit device are respectively formed in these first and second device forming regions. The output circuit device is a conductivity modulated MOS transistor having the p.sup.+ -type substrate as a drain and the second device forming regoin as a high resistance region whose conductivity is modulated.

摘要翻译： 存在一种半导体器件，其中形成在p +型衬底上的n型层通过隔离区域分成第一和第二器件形成区域，并且驱动电路器件和输出电路器件分别形成在这些第一和第二器件中 形成区域。 输出电路器件是具有p +型衬底作为漏极的导电调制MOS晶体管，并且第二器件形成引线作为其电导率被调制的高电阻区域。

公开(公告)号：US4855799A

公开(公告)日：1989-08-08

申请号：US136767

申请日：1987-12-22

申请人： Hirohito Tanabe ,  Yu Ohata ,  Kazuaki Suzuki ,  Yukiharu Miwa ,  Yoshihito Nakayama

发明人： Hirohito Tanabe ,  Yu Ohata ,  Kazuaki Suzuki ,  Yukiharu Miwa ,  Yoshihito Nakayama

IPC分类号： H01L21/22 ,  H01L21/336 ,  H01L29/167 ,  H01L29/45 ,  H01L29/78

CPC分类号： H01L29/66712 ,  H01L21/221 ,  H01L29/167 ,  H01L29/7805 ,  H01L29/7813 ,  H01L29/4236 ,  H01L29/456

摘要： In a power MOS FET and the method of manufacturing such FET, in which a material, such as platinum, having a small resistivity compensation effect is diffused as a lifetime killer into the vicinity of a PN diode junction formed by the drain region and the base region. The diffusion is made through an opening formed in a covering insulator layer. An example of the lifetime killer is platinum and the preferable temperature range for diffusing platinum is not higher than 900.degree. C.

摘要翻译： 在功率MOS FET和制造这种FET的方法中，其中具有小电阻率补偿效应的诸如铂的材料作为寿命抑制剂扩散到由漏极区域和基极形成的PN二极管结附近 地区。 通过形成在覆盖绝缘体层中的开口进行扩散。 寿命杀手的一个例子是铂，扩散铂的优选温度范围不高于900℃。

公开(公告)号：US4777149A

公开(公告)日：1988-10-11

申请号：US136770

申请日：1987-12-22

申请人： Hirohito Tanabe ,  Yu Ohata ,  Kazuaki Suzuki ,  Yukiharu Miwa ,  Yoshihito Nakayama

发明人： Hirohito Tanabe ,  Yu Ohata ,  Kazuaki Suzuki ,  Yukiharu Miwa ,  Yoshihito Nakayama

IPC分类号： H01L21/336 ,  H01L29/167 ,  H01L29/78 ,  H01L21/383

CPC分类号： H01L29/66712 ,  H01L21/221 ,  H01L29/167 ,  H01L29/66734 ,  H01L29/7805 ,  H01L29/7813 ,  H01L29/4236 ,  H01L29/456 ,  Y10S438/904

摘要： In a power MOS FET and the method of manufacturing such FET, in which a material, such as platinum, having a small resistivity compensation effect is diffused as a lifetime killer into the vicinity of a PN diode junction formed by the drain region and the base region. The diffusion is made through an opening formed in a covering insulator layer. An example of the lifetime killer is platinum and the preferable temperature range for diffusing platinum is not higher than 900.degree.C.

摘要翻译： 在功率MOS FET和制造这种FET的方法中，其中具有小电阻率补偿效应的诸如铂的材料作为寿命抑制剂扩散到由漏极区域和基极形成的PN二极管结附近 地区。 通过形成在覆盖绝缘体层中的开口进行扩散。 寿命杀手的一个例子是铂，扩散铂的优选温度范围不高于900℃。