公开(公告)号：US6136695A

公开(公告)日：2000-10-24

申请号：US366741

申请日：1999-08-04

申请人： Yu-Hua Lee ,  Cheng-Ming Wu ,  Ming-Hsiung Chiang

发明人： Yu-Hua Lee ,  Cheng-Ming Wu ,  Ming-Hsiung Chiang

IPC分类号： H01L21/314 ,  H01L21/60 ,  H01L21/4763

CPC分类号： H01L21/76831 ,  H01L21/76897 ,  H01L21/3144

摘要： A method for forming a self aligned contact wherein a dielectric layer is formed directly on a conductive structure according the present invention. A semiconductor structure having a polysilicon conductive structure (such as a bit line) thereon is provided. A contact area is located on the semiconductor structure adjacent to the conductive structure. A dielectric layer, preferably composed of silicon oxide is formed over the conductive structure and the semiconductor structure. A top hard mask layer is formed over the dielectric layer. A contact opening is formed in the top hard mask layer and the dielectric layer using an etch selective to oxide over polysilicon, thereby exposing the contact region of the semiconductor structure adjacent to the conductive structure without etching through the conductive structure. A first lining dielectric layer, a second lining dielectric layer, and a third lining dielectric layer are sequentially deposited on the sidewalls of the contact opening and on the contact area of the semiconductor structure. The first and third lining dielectric layers are preferably composed of silicon dioxide and the third lining dielectric layer is preferably composed of silicon nitride. The third lining dielectric layer is anisotropically etched forming a second contact opening in the second lining dielectric layer over the contact area while leaving a spacer on the sidewall of the contact opening. The second lining dielectric layer and the first lining dielectric layer are anisotropically etched to expose the contact area of the semiconductor structure, while the spacer prevents erosion of the second lining dielectric layer and the first lining dielectric layer on the sidewall of the contact opening. The remaining spacer is removed, preferably using a buffered HF dip. A polysilicon contact layer is formed on the second lining dielectric layer and on the contact area of the semiconductor structure.

摘要翻译： 一种形成自对准接触的方法，其中介电层直接形成在根据本发明的导电结构上。 提供具有多晶硅导电结构（例如位线）的半导体结构。 接触区域位于与导电结构相邻的半导体结构上。 在导电结构和半导体结构之上形成优选由氧化硅构成的电介质层。 在电介质层上方形成顶部硬掩模层。 在顶部硬掩模层和电介质层中使用对多晶硅上的氧化物的选择性蚀刻形成接触开口，由此暴露出与导电结构相邻的半导体结构的接触区域而不通过导电结构进行蚀刻。 第一衬里介电层，第二衬里电介质层和第三衬里电介质层依次沉积在接触开口的侧壁和半导体结构的接触区域上。 第一和第三衬里电介质层优选由二氧化硅构成，第三衬里电介质层优选由氮化硅构成。 第三衬里电介质层被各向异性蚀刻，在接触区域上形成第二衬里介电层中的第二接触开口，同时在接触开口的侧壁上留下间隔物。 第二衬里电介质层和第一衬里电介质层被各向异性蚀刻以暴露半导体结构的接触面积，而间隔物防止第二衬里介电层和接触开口侧壁上的第一衬里介电层的侵蚀。 除去剩余的间隔物，优选使用缓冲的HF浸渍。 在第二衬里电介质层和半导体结构的接触区域上形成多晶硅接触层。

公开(公告)号：US06168989A

公开(公告)日：2001-01-02

申请号：US09318924

申请日：1999-05-26

申请人： Ming-Hsiung Chiang ,  Wen-Chuan Chiang ,  Cheng-Ming Wu

发明人： Ming-Hsiung Chiang ,  Wen-Chuan Chiang ,  Cheng-Ming Wu

IPC分类号： H01L218242

CPC分类号： H01L28/91 ,  H01L27/10814

摘要： A method for making crown capacitors using a new and improved crown etch window process for DRAM cells is described. After forming FETs for the memory cells, a planar first insulating layer (IPO-1) is formed and bit lines are formed thereon. A second insulating layer (IPO-2) is deposited, and a first etch-stop layer and a disposable insulating layer are deposited. Contact openings are etched in the layers to the substrate, and are filled with a polysilicon to form capacitor node contact plugs. The disposable layer is removed to expose the upper portions of the plugs extending above the first etch-stop layer. A second etch-stop layer is deposited and a thick insulating layer is deposited in which capacitor openings are etched over and to the plugs. The capacitor openings can be over-etched in the thick insulating layer because the plugs extend upward thereby allowing all the plugs to be exposed across the wafer without overetching the underlying IPO-2 layer that would otherwise cause capacitor-to-bit-line shorts when the bottom electrodes are formed in the capacitor openings.

摘要翻译： 描述了使用用于DRAM单元的新的和改进的冠蚀刻窗口工艺制造冠电容器的方法。 在形成用于存储单元的FET之后，形成平面的第一绝缘层（IPO-1），并在其上形成位线。 沉积第二绝缘层（IPO-2），并沉积第一蚀刻停止层和一次性绝缘层。 接触开口在层中蚀刻到衬底上，并且填充有多晶硅以形成电容器节点接触插塞。 去除一次性层以暴露在第一蚀刻停止层上方延伸的插塞的上部。 沉积第二蚀刻停止层，并且沉积厚的绝缘层，其中电容器开口被蚀刻到插头上。 电容器开口可以在厚的绝缘层中过蚀刻，因为插头向上延伸，从而允许所有的插头暴露在晶片上，而不会过滤掉底层的IPO-2层，否则会导致电容器对位线短路， 底部电极形成在电容器开口中。

公开(公告)号：US6143604A

公开(公告)日：2000-11-07

申请号：US325956

申请日：1999-06-04

申请人： Ming-Hsiung Chiang ,  Wen-Chuan Chiang ,  Cheng-Ming Wu

发明人： Ming-Hsiung Chiang ,  Wen-Chuan Chiang ,  Cheng-Ming Wu

IPC分类号： H01L21/311 ,  H01L21/60 ,  H01L21/8242

CPC分类号： H01L27/10891 ,  H01L21/76897 ,  H01L21/31116 ,  H01L21/31144 ,  H01L27/10852

摘要： A method using a two-step contact process for making word-line strapping on DRAM devices was achieved. The method replaces a single-step contact process in which it is difficult to etch the smaller contact openings. After partially completing the DRAM cells by forming gate electrodes and word lines having a first hard mask, a planar first insulating layer is formed. Capacitor node contact openings are etched and capacitors with a protective second hard mask are completed. A thin first photoresist mask with improved resolution is used to etch small first contact openings in the first insulating layer to the word lines, while the second hard mask protects the capacitors from etching. Tungsten plugs are formed in the openings, and an interlevel dielectric layer is deposited over the capacitors. A thin second photoresist mask with improved resolution is used to etch second contact openings to the tungsten plugs. The word-line strapping for the DRAM is completed by forming tungsten plugs in the second contact openings. Since the tungsten plugs are formed after forming the capacitors, they are not subjected to high-temperature processing that could adversely affect the DRAM devices. The two thin photoresist masks replacing a thicker photoresist mask used in the single-step process allow smaller contact openings to be etched.

摘要翻译： 实现了使用两步接触工艺在DRAM器件上进行字线捆扎的方法。 该方法代替难以蚀刻较小接触开口的单步接触过程。 在通过形成具有第一硬掩模的栅电极和字线部分地完成DRAM单元之后，形成平面的第一绝缘层。 蚀刻电容器节点接触开口并完成具有保护性第二硬掩模的电容器。 使用具有改进的分辨率的薄的第一光致抗蚀剂掩模来将第一绝缘层中的小的第一接触开口蚀刻到字线，而第二硬掩模保护电容器免受蚀刻。 在开口中形成钨塞，并且在电容器上沉积层间电介质层。 使用具有改进的分辨率的薄的第二光致抗蚀剂掩模来蚀刻到钨插塞的第二接触开口。 通过在第二接触开口中形成钨插塞来完成DRAM的字线捆扎。 由于在形成电容器之后形成钨插塞，所以不会对可能对DRAM器件产生不利影响的高温处理。 替代在单步法中使用的较厚的光致抗蚀剂掩模的两个薄的光致抗蚀剂掩模允许蚀刻更小的接触开口。

公开(公告)号：US06168984A

公开(公告)日：2001-01-02

申请号：US09419103

申请日：1999-10-15

申请人： Chue-San Yoo ,  Ming-Hsiung Chiang ,  Wen-Chuan Chiang ,  Cheng-Ming Wu ,  Tse-Liang Ying

发明人： Chue-San Yoo ,  Ming-Hsiung Chiang ,  Wen-Chuan Chiang ,  Cheng-Ming Wu ,  Tse-Liang Ying

IPC分类号： H01L218242

CPC分类号： H01L27/10888 ,  H01L27/10814 ,  H01L27/10894 ,  H01L28/84 ,  H01L28/91

摘要： A process for reducing the aspect ratio, for narrow diameter contact holes, formed in thick insulator layers, used to integrate logic and DRAM memory devices, on the same semiconductor chip, has been developed. The process of reducing the aspect ratio, of these contact holes, features initially forming, via patterning procedures, lower, narrow diameter contact holes, to active device regions, in the logic area, while also forming self-aligned contact openings to source/drain regions in the DRAM memory region. After forming tungsten structures, in the lower, narrow diameter contact holes, polycide bitline, and polysilicon capacitor structures, are formed in the DRAM memory region, via deposition, and patterning, of upper level insulator layers, and polysilicon and polycide conductive layers. Upper, narrow diameter openings, are then formed in the upper level insulator layers, exposing the top surface of tungsten structures, located in the lower, narrow diameter contact holes. The formation of upper tungsten structures, in the upper, narrow diameter contact openings completes the process of forming metal structures, in narrow diameter openings, with reduced aspect ratios, achieved via a two stage contact hole opening, and a two stage metal filling procedure.

摘要翻译： 已经开发了用于在相同的半导体芯片上将用于集成逻辑和DRAM存储器件的厚的绝缘体层中形成的窄直径接触孔的宽高比减小的方法。 减小这些接触孔的纵横比的过程，其特征在于，通过图案化步骤，在逻辑区域中最初形成较小的窄直径的接触孔到有源器件区域，同时还形成自对准的接触开口到源极/漏极 DRAM存储区域中的区域。 在形成钨结构之后，在下部窄直径的接触孔中，多晶硅位线和多晶硅电容器结构通过上层绝缘体层和多晶硅和多晶硅导电层的沉积和图案形成在DRAM存储区域中。 然后在上层绝缘体层中形成上部，小直径的开口，暴露位于下部较窄直径的接触孔中的钨结构的顶表面。 在上部窄直径接触开口中形成上部钨结构完成了通过两级接触孔开口形成的具有减小的纵横比的窄直径开口中的金属结构的形成和两阶段金属填充程序的过程。

公开(公告)号：US06555435B2

公开(公告)日：2003-04-29

申请号：US10087070

申请日：2002-03-01

申请人： Ming-Hsiung Chiang ,  James Wu ,  Yu-Hua Lee

发明人： Ming-Hsiung Chiang ,  James Wu ,  Yu-Hua Lee

IPC分类号： H01L2336

CPC分类号： H01L21/76831 ,  H01L21/76897

摘要： A method to form contacts in an integrated circuit device comprising to eliminate shorting between adjacent contacts due to dielectric layer voids is achieved. A substrate is provided. Narrowly spaced conductive lines are provided on the substrate. A dielectric layer is deposited overlying the conductive lines and the substrate. The dielectric layer is etched through to the top surface of the substrate in areas defined by lithographic mask to form contact openings between adjacent narrowly spaced conductive lines. An insulating layer is deposited overlying the dielectric layer and filling the contact openings wherein the insulating layer forms a lining layer inside the contact openings and fills any voids in the dielectric layer extending out of the contact openings. The insulating layer is etched through to expose the top surface of the substrate. A conductive layer is deposited overlying the dielectric layer and filling the contact openings. The conductive layer is etched as defined by lithographic mask. A passivation layer is deposited overlying the conductive layer and the dielectric layer. The integrated circuit device is completed.

公开(公告)号：US06365464B1

公开(公告)日：2002-04-02

申请号：US09318470

申请日：1999-05-25

申请人： Ming-Hsiung Chiang ,  James Wu ,  Yu-Hua Lee

发明人： Ming-Hsiung Chiang ,  James Wu ,  Yu-Hua Lee

IPC分类号： H10L21336

CPC分类号： H01L21/76831 ,  H01L21/76897

摘要： A method to form contacts in an integrated circuit device comprising to eliminate shorting between adjacent contacts due to dielectric layer voids is achieved. A substrate is provided. Narrowly spaced conductive lines are provided on the substrate. A dielectric layer is deposited overlying the conductive lines and the substrate. The dielectric layer is etched through to the top surface of the substrate in areas defined by lithographic mask to form contact openings between adjacent narrowly spaced conductive lines. An insulating layer is deposited overlying the dielectric layer and filling the contact openings wherein the insulating layer forms a lining layer inside the contact openings and fills any voids in the dielectric layer extending out of the contact openings. The insulating layer is etched through to expose the top surface of the substrate. A conductive layer is deposited overlying the dielectric layer and filling the contact openings. The conductive layer is etched as defined by lithographic mask. A passivation layer is deposited overlying the conductive layer and the dielectric layer. The integrated circuit device is completed.

摘要翻译： 在集成电路器件中形成接触的方法包括消除由于电介质层空隙引起的相邻触点之间的短路。 提供基板。 在基板上设置窄间隔的导线。 沉积覆盖导电线和衬底的电介质层。 在由光刻掩模限定的区域中，将介电层蚀刻到衬底的顶表面，以在相邻的窄间隔的导线之间形成接触开口。 绝缘层沉积在电介质层上方并填充接触开口，其中绝缘层在接触开口内形成衬里层，并填充延伸出接触开口的电介质层中的任何空隙。 蚀刻绝缘层以暴露衬底的顶表面。 沉积覆盖介电层并填充接触开口的导电层。 如由光刻掩模所限定的那样蚀刻导电层。 沉积覆盖在导电层和电介质层上的钝化层。 集成电路装置完成。