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1.发明授权Reduction of the aspect ratio of deep contact holes for embedded DRAM devices 有权降低嵌入式DRAM器件深度接触孔的长宽比公开(公告)号：US06168984A
公开(公告)日：2001-01-02
申请号：US09419103
申请日：1999-10-15
IPC分类号： H01L218242
CPC分类号： H01L27/10888 , H01L27/10814 , H01L27/10894 , H01L28/84 , H01L28/91
摘要： A process for reducing the aspect ratio, for narrow diameter contact holes, formed in thick insulator layers, used to integrate logic and DRAM memory devices, on the same semiconductor chip, has been developed. The process of reducing the aspect ratio, of these contact holes, features initially forming, via patterning procedures, lower, narrow diameter contact holes, to active device regions, in the logic area, while also forming self-aligned contact openings to source/drain regions in the DRAM memory region. After forming tungsten structures, in the lower, narrow diameter contact holes, polycide bitline, and polysilicon capacitor structures, are formed in the DRAM memory region, via deposition, and patterning, of upper level insulator layers, and polysilicon and polycide conductive layers. Upper, narrow diameter openings, are then formed in the upper level insulator layers, exposing the top surface of tungsten structures, located in the lower, narrow diameter contact holes. The formation of upper tungsten structures, in the upper, narrow diameter contact openings completes the process of forming metal structures, in narrow diameter openings, with reduced aspect ratios, achieved via a two stage contact hole opening, and a two stage metal filling procedure.
摘要翻译： 已经开发了用于在相同的半导体芯片上将用于集成逻辑和DRAM存储器件的厚的绝缘体层中形成的窄直径接触孔的宽高比减小的方法。 减小这些接触孔的纵横比的过程，其特征在于，通过图案化步骤，在逻辑区域中最初形成较小的窄直径的接触孔到有源器件区域，同时还形成自对准的接触开口到源极/漏极 DRAM存储区域中的区域。 在形成钨结构之后，在下部窄直径的接触孔中，多晶硅位线和多晶硅电容器结构通过上层绝缘体层和多晶硅和多晶硅导电层的沉积和图案形成在DRAM存储区域中。 然后在上层绝缘体层中形成上部，小直径的开口，暴露位于下部较窄直径的接触孔中的钨结构的顶表面。 在上部窄直径接触开口中形成上部钨结构完成了通过两级接触孔开口形成的具有减小的纵横比的窄直径开口中的金属结构的形成和两阶段金属填充程序的过程。
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2.发明授权Method for fabricating small-size two-step contacts for word-line strapping on dynamic random access memory (DRAM) 有权用于在动态随机存取存储器（DRAM）上制造用于字线捆扎的小尺寸两步触点的方法
公开(公告)号：US6143604A
公开(公告)日：2000-11-07
申请号：US325956
申请日：1999-06-04
IPC分类号： H01L21/311 , H01L21/60 , H01L21/8242
CPC分类号： H01L27/10891 , H01L21/76897 , H01L21/31116 , H01L21/31144 , H01L27/10852
摘要： A method using a two-step contact process for making word-line strapping on DRAM devices was achieved. The method replaces a single-step contact process in which it is difficult to etch the smaller contact openings. After partially completing the DRAM cells by forming gate electrodes and word lines having a first hard mask, a planar first insulating layer is formed. Capacitor node contact openings are etched and capacitors with a protective second hard mask are completed. A thin first photoresist mask with improved resolution is used to etch small first contact openings in the first insulating layer to the word lines, while the second hard mask protects the capacitors from etching. Tungsten plugs are formed in the openings, and an interlevel dielectric layer is deposited over the capacitors. A thin second photoresist mask with improved resolution is used to etch second contact openings to the tungsten plugs. The word-line strapping for the DRAM is completed by forming tungsten plugs in the second contact openings. Since the tungsten plugs are formed after forming the capacitors, they are not subjected to high-temperature processing that could adversely affect the DRAM devices. The two thin photoresist masks replacing a thicker photoresist mask used in the single-step process allow smaller contact openings to be etched.
摘要翻译： 实现了使用两步接触工艺在DRAM器件上进行字线捆扎的方法。 该方法代替难以蚀刻较小接触开口的单步接触过程。 在通过形成具有第一硬掩模的栅电极和字线部分地完成DRAM单元之后，形成平面的第一绝缘层。 蚀刻电容器节点接触开口并完成具有保护性第二硬掩模的电容器。 使用具有改进的分辨率的薄的第一光致抗蚀剂掩模来将第一绝缘层中的小的第一接触开口蚀刻到字线，而第二硬掩模保护电容器免受蚀刻。 在开口中形成钨塞，并且在电容器上沉积层间电介质层。 使用具有改进的分辨率的薄的第二光致抗蚀剂掩模来蚀刻到钨插塞的第二接触开口。 通过在第二接触开口中形成钨插塞来完成DRAM的字线捆扎。 由于在形成电容器之后形成钨插塞，所以不会对可能对DRAM器件产生不利影响的高温处理。 替代在单步法中使用的较厚的光致抗蚀剂掩模的两个薄的光致抗蚀剂掩模允许蚀刻更小的接触开口。
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3.发明授权Process for making new and improved crown-shaped capacitors on dynamic random access memory cells 有权在动态随机存取存储器单元上制造新的和改进的冠状电容器的方法公开(公告)号：US06168989A
公开(公告)日：2001-01-02
申请号：US09318924
申请日：1999-05-26
IPC分类号： H01L218242
CPC分类号： H01L28/91 , H01L27/10814
摘要： A method for making crown capacitors using a new and improved crown etch window process for DRAM cells is described. After forming FETs for the memory cells, a planar first insulating layer (IPO-1) is formed and bit lines are formed thereon. A second insulating layer (IPO-2) is deposited, and a first etch-stop layer and a disposable insulating layer are deposited. Contact openings are etched in the layers to the substrate, and are filled with a polysilicon to form capacitor node contact plugs. The disposable layer is removed to expose the upper portions of the plugs extending above the first etch-stop layer. A second etch-stop layer is deposited and a thick insulating layer is deposited in which capacitor openings are etched over and to the plugs. The capacitor openings can be over-etched in the thick insulating layer because the plugs extend upward thereby allowing all the plugs to be exposed across the wafer without overetching the underlying IPO-2 layer that would otherwise cause capacitor-to-bit-line shorts when the bottom electrodes are formed in the capacitor openings.
摘要翻译： 描述了使用用于DRAM单元的新的和改进的冠蚀刻窗口工艺制造冠电容器的方法。 在形成用于存储单元的FET之后，形成平面的第一绝缘层（IPO-1），并在其上形成位线。 沉积第二绝缘层（IPO-2），并沉积第一蚀刻停止层和一次性绝缘层。 接触开口在层中蚀刻到衬底上，并且填充有多晶硅以形成电容器节点接触插塞。 去除一次性层以暴露在第一蚀刻停止层上方延伸的插塞的上部。 沉积第二蚀刻停止层，并且沉积厚的绝缘层，其中电容器开口被蚀刻到插头上。 电容器开口可以在厚的绝缘层中过蚀刻，因为插头向上延伸，从而允许所有的插头暴露在晶片上，而不会过滤掉底层的IPO-2层，否则会导致电容器对位线短路， 底部电极形成在电容器开口中。
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4.发明授权Method for making a double-cylinder-capacitor structure for dynamic random access memory (DRAM) 有权制造用于动态随机存取存储器（DRAM）的双缸电容器结构的方法公开(公告)号：US06403416B1
公开(公告)日：2002-06-11
申请号：US09226279
申请日：1999-01-07
IPC分类号： H01L218242
CPC分类号： H01L28/91
摘要： A method using a single masking step for making double-cylinder stacked capacitors for DRAMs which increases capacitance while eliminating erosion of an underlying oxide insulating layer when the masking step is misaligned is described. A planar silicon oxide (SiO2) first insulating layer is formed over device areas, and a first silicon nitride (Si3N4) etch-stop layer is deposited, and openings are etched for capacitor node contacts. A first polysilicon layer is deposited to a thickness sufficient to fill the openings and to form an essentially planar surface. A second insulating layer is deposited and patterned to form portions with vertical sidewalls over the node contacts. A conformal second Si3N4 layer is deposited and etched back to form spacers on the vertical sidewalls, and the first polysilicon layer is etched to the first Si3N4 layer. The second insulating layer is selectively removed using HF acid while the first polysilicon and first Si3N4 layers prevent etching of the underlying first SiO2 layer. A second polysilicon layer is deposited and etched back to form double-cylinder sidewalls for the capacitor bottom electrodes. The first and second Si3N4 layers are removed in hot phosphoric acid. The capacitors are completed by forming an interelectrode dielectric layer on the bottom electrodes, and depositing a third polysilicon layer for top electrodes.
摘要翻译： 描述了一种使用单个掩模步骤来制造用于DRAM的双圆柱体堆叠电容器的方法，其在掩蔽步骤未对准时消除了下面的氧化物绝缘层的侵蚀，同时增加了电容。 在器件区域上形成平面氧化硅（SiO 2）第一绝缘层，并沉积第一氮化硅（Si 3 N 4）蚀刻停止层，并且蚀刻用于电容器节点接触的开口。 第一多晶硅层被沉积到足以填充开口并形成基本平坦的表面的厚度。 沉积和图案化第二绝缘层以在节点接触件上形成具有垂直侧壁的部分。 沉积保形第二Si 3 N 4层并回蚀刻以在垂直侧壁上形成间隔物，并且将第一多晶硅层蚀刻到第一Si 3 N 4层。 使用HF酸选择性地除去第二绝缘层，而第一多晶硅和第一Si 3 N 4层防止蚀刻下面的第一SiO 2层。 沉积第二多晶硅层并将其回蚀以形成用于电容器底部电极的双气缸侧壁。 在热磷酸中除去第一和第二Si 3 N 4层。 电容器通过在底部电极上形成电极间电介质层而形成，并且为顶部电极沉积第三多晶硅层。
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5.发明授权Key-hole free process for high aspect ratio gap filling with reentrant spacer 有权无缝隙工艺，用于高长宽比间隙填充可重入间隔公开(公告)号：US07482278B1
公开(公告)日：2009-01-27
申请号：US09247974
申请日：1999-02-11
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , H01L21/31056 , H01L21/76837
摘要： A new method of depositing PE-oxide or PE-TEOS. An HDP-oxide is provided over a pattern of polysilicon. An etch back is performed to the deposited HDP-oxide, a layer of plasma-enhanced SiN is deposited. This PE-SiN is etched back leaving SiN spacers on the sidewalls of the poly pattern, further leaving a deposition of HDP-oxide on the top surface of the poly pattern. The profile of the holes within the poly pattern in such that the final layer of PE-oxide or PE-TEOS is deposited without resulting in the formation of keyholes in this latter layer.
摘要翻译： 一种沉积PE氧化物或PE-TEOS的新方法。 在多晶硅图案上提供HDP氧化物。 对沉积的HDP-氧化物进行回蚀刻，沉积一层等离子体增强的SiN。 该PE-SiN被回蚀刻，留下多边形图案的侧壁上的SiN间隔物，进一步在多晶型图案的顶表面上留下HDP氧化物。 多晶型图案中的孔的轮廓使得沉积最终的聚乙烯氧化物层或PE-TEOS层，而不会在后一层中形成键槽。
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6.发明授权Node process integration technology to improve data retention for logic based embedded dram 有权节点过程集成技术，以提高基于逻辑的嵌入式电脑的数据保留公开(公告)号：US06187659B1
公开(公告)日：2001-02-13
申请号：US09368861
申请日：1999-08-06
申请人： Tse-Liang Ying , Wen-Chuan Chiang , Cheng-Ming Wu , Yu-Hua Lee
发明人： Tse-Liang Ying , Wen-Chuan Chiang , Cheng-Ming Wu , Yu-Hua Lee
IPC分类号： H01L214763
CPC分类号： H01L27/10855 , H01L21/28525 , H01L21/76877 , H01L21/76885 , H01L21/76897
摘要： A new method is provided to create a gradated dopant concentration in the contact plug of DRAM devices whereby a high dopant concentration is present at the bottom of the plug and a low dopant concentration is present at the top of the plug. Two layers of dielectric are deposited; the upper layer serves as a layer to adjust the dopant concentration in the lower layer. This adjustment is done by Rapid Thermal anneal of both layers of dielectric. After the dopant concentration has been adjusted, the upper layer of dielectric is removed and the upper section of the contact node is formed using lightly doped poly. The high dopant concentration at the bottom of the contact plug results in low contact resistance between the plug and the underlying silicon substrate. A low dopant concentration at the top surface of the contact plug results in low oxidation of the surface of the plug.
摘要翻译： 提供了一种新的方法来在DRAM器件的接触插塞中产生渐变的掺杂剂浓度，由此在插塞的底部存在高的掺杂剂浓度，并且在插头的顶部存在低的掺杂剂浓度。 沉积两层电介质; 上层用作调整下层中的掺杂剂浓度的层。 这种调整是通过两层电介质的快速热退火进行的。 在调整掺杂剂浓度之后，去除电介质的上层，并且使用轻掺杂的多晶形成接触节点的上部。 接触插塞底部的高掺杂剂浓度导致插头和底层硅衬底之间的低接触电阻。 在接触塞顶表面的低掺杂剂浓度导致插塞表面的低氧化。
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7.发明授权Process to fabricate a cylindrical, capacitor structure under a bit line structure for a dynamic random access memory cell 失效在用于动态随机存取存储器单元的位线结构下制造圆柱形电容器结构的工艺
公开(公告)号：US6165839A
公开(公告)日：2000-12-26
申请号：US92880
申请日：1998-06-08
申请人： Yu-Hua Lee , Cheng-Ming Wu , Wen-Chuan Chiang
发明人： Yu-Hua Lee , Cheng-Ming Wu , Wen-Chuan Chiang
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10888 , H01L27/10811 , H01L28/91
摘要： A process for forming a DRAM, cylindrical shaped, stacked capacitor structure, located under a bit line structure, has been developed. The process features defining a polysilicon cell plate structure, during the same photolithotgraphic and anisotropic etching procedures, used to open a bit line contact hole. The bit line contact hole is formed by first opening a top portion of the bit line contact hole, using a photoresist shape as an etch mask, and after the formation of silicon nitride spacers, on the sides of the top portion of the bit line contact hole, the bottom portion of the bit line contact hole is opened, using silicon nitride as an etch mask.
摘要翻译： 已经开发了一种用于形成位于位线结构下方的DRAM，圆柱形，堆叠式电容器结构的工艺。 在用于打开位线接触孔的相同的光电影和各向异性蚀刻过程中，限定多晶硅单元板结构的过程特征。 位线接触孔通过使用光致抗蚀剂形状作为蚀刻掩模首先打开位线接触孔的顶部，并且在形成氮化硅间隔物之后，在位线接触的顶部的侧面 使用氮化硅作为蚀刻掩模，打开位线接触孔的底部。
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公开(公告)号：US06103455A
公开(公告)日：2000-08-15
申请号：US73947
申请日：1998-05-07
申请人： Kuo Ching Huang , Wen-Chuan Chiang , Cheng-Ming Wu , Yu-Hua Lee
发明人： Kuo Ching Huang , Wen-Chuan Chiang , Cheng-Ming Wu , Yu-Hua Lee
IPC分类号： H01L21/768 , G03F7/26
CPC分类号： H01L21/76876 , H01L21/76802 , H01L21/7684 , H01L21/76843 , H01L21/7688
摘要： A method of forming a deep contact by forming a dielectric layer 20 over a semiconductor structure 10. A main point is that the hard mask 30 is removed after the plug 52 is formed. A hard mask layer 30 is formed over the dielectric layer 20. A contact photoresist layer 36 is formed over the hard mask layer 30. The hard mask layer 30 is etched through the contact photoresist opening 39 to form a contact hard mask opening 41 exposing the dielectric layer 20. The dielectric layer 20 is etched using a high density plasma etch process using the contact photoresist layer 36 and the hard mask layer 30 as an etch mask forming a contact hole 40 in the dielectric layer 20. The contact photoresist layer 36 is removed. A metal layer 50 is formed filling the contact hole 40 and covering over the hard mask layer 30. The metal layer 50 is etched back forming a plug 52 filling the contact hole 40. Now, the hard mask layer 30 is removed. The removal of the hard mask 30 after the metal layer 50 deposition: (a) prevents the contact hole 40 from being contaminated from photoresist and other contamination formed during the hard mask 30 removal steps; and (b) creates a plug 52 that does not have a recess.
摘要翻译： 通过在半导体结构10上形成电介质层20来形成深度接触的方法。主要的一点是在形成插头52之后去除硬掩模30。 在电介质层20上形成硬掩模层30.在硬掩模层30之上形成接触光刻胶层36.硬掩模层30通过接触光致抗蚀剂开口39蚀刻以形成接触硬掩模开口41， 电介质层20.使用接触光致抗蚀剂层36和硬掩模层30作为在电介质层20中形成接触孔40的蚀刻掩模的高密度等离子体蚀刻工艺来蚀刻电介质层20.接触光致抗蚀剂层36是 删除。 形成填充接触孔40并覆盖在硬掩模层30上的金属层50.金属层50被回蚀，形成填充接触孔40的插塞52.现在，去除硬掩模层30。 在金属层50沉积之后去除硬掩模30：（a）防止接触孔40在硬掩模30去除步骤期间被光致抗蚀剂和其它污染物污染; 和（b）产生不具有凹部的插头52。
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9.发明授权公开(公告)号：US06235580B1
公开(公告)日：2001-05-22
申请号：US09467123
申请日：1999-12-20
申请人： Yu-Hua Lee , Cheng-Ming Wu , Wen-Chuan Chiang
发明人： Yu-Hua Lee , Cheng-Ming Wu , Wen-Chuan Chiang
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L28/91
摘要： A process for forming crown shaped capacitor structures, for a DRAM device, has been developed. The process features the use of a disposable insulator layer, applied prior to photolithographic and dry etching procedures, used to define the capacitor upper plate structures. The disposable insulator layer alleviates the topography effects presented by crown shaped storage node structures, relaxing the complexity of the patterning of the capacitor upper plate structures.
摘要翻译： 已经开发了用于形成用于DRAM器件的冠形电容器结构的工艺。 该方法的特征在于使用一次性绝缘体层，其在光刻和干蚀刻工艺之前施加，用于限定电容器上板结构。 一次性绝缘体层减轻了冠形存储节点结构呈现的形貌效应，减轻了电容器上板结构图案化的复杂性。
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公开(公告)号：US08617949B2
公开(公告)日：2013-12-31
申请号：US13267424
申请日：2011-10-06
申请人： Kuo-Chi Tu , Wen-Chuan Chiang , Chen-Jong Wang
发明人： Kuo-Chi Tu , Wen-Chuan Chiang , Chen-Jong Wang
IPC分类号： H01L21/8242
CPC分类号： H01L28/60 , H01L23/5223 , H01L27/105 , H01L27/1052 , H01L27/108 , H01L27/10894 , H01L27/11 , H01L27/1116 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A system-on-chip device comprises a first capacitor in a first region, a second capacitor in a second region, and may further comprise a third capacitor in a third region, and any additional number of capacitors in additional regions. The capacitors may be of different shapes and sizes. A region may comprise more than one capacitor. Each capacitor in a region has a top electrode, a bottom electrode, and a capacitor insulator. The top electrodes of all the capacitors are formed in a common process, while the bottom electrodes of all the capacitors are formed in a common process. The capacitor insulator may have different number of sub-layers, formed with different materials or thickness. The capacitors may be formed in an inter-layer dielectric layer or in an inter-metal dielectric layer. The regions may be a mixed signal region, an analog region, and so forth.
摘要翻译： 片上系统装置包括第一区域中的第一电容器，第二区域中的第二电容器，并且还可以包括第三区域中的第三电容器，以及附加区域中的任何附加数量的电容器。 电容器可以具有不同的形状和尺寸。 区域可以包括多于一个的电容器。 区域中的每个电容器具有顶部电极，底部电极和电容器绝缘体。 所有电容器的顶部电极以公共工艺形成，而所有电容器的底部电极形成在共同的工艺中。 电容器绝缘体可以具有不同数量的亚层，形成不同的材料或厚度。 电容器可以形成在层间电介质层中或在金属间介电层中。 这些区域可以是混合信号区域，模拟区域等。
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