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    Mechanisms of doping oxide for forming shallow trench isolation
    1.
    发明授权
    Mechanisms of doping oxide for forming shallow trench isolation 有权
    掺杂氧化物形成浅沟槽隔离的机理

    公开(公告)号：US08877602B2

    公开(公告)日：2014-11-04

    申请号：US13156939

    申请日：2011-06-09

    申请人： Yu-Lien Huang ,  Chun Hsiung Tsai ,  Chii-Ming Wu ,  Ziwei Fang

    发明人： Yu-Lien Huang ,  Chun Hsiung Tsai ,  Chii-Ming Wu ,  Ziwei Fang

    IPC分类号： H01L21/76 ,  H01L21/762

    CPC分类号： H01L21/76229

    摘要： The embodiments described provide mechanisms for doping oxide in the STIs with carbon to make etch rate in the narrow and wide structures equal and also to make corners of wide STIs strong. Such carbon doping can be performed by ion beam (ion implant) or by plasma doping. The hard mask layer can be used to protect the silicon underneath from doping. By using the doping mechanism, the even surface topography of silicon and STI enables patterning of gate structures and ILD0 gapfill for advanced processing technology.

    摘要翻译： 所描述的实施例提供了用碳掺杂STI中的氧化物的机制，以使窄和宽结构中的蚀刻速率相等并且也使得宽STI的拐角变强。 这种碳掺杂可以通过离子束（离子注入）或通过等离子体掺杂来进行。 硬掩模层可用于保护下面的硅不被掺杂。 通过使用掺杂机制，硅和STI的均匀表面形貌使得门结构和ILD0间隙填充的图案化能够用于先进的加工技术。

    Doped oxide for shallow trench isolation (STI)
    2.
    发明授权
    Doped oxide for shallow trench isolation (STI) 有权
    用于浅沟槽隔离（STI）的掺杂氧化物

    公开(公告)号：US08592915B2

    公开(公告)日：2013-11-26

    申请号：US13012948

    申请日：2011-01-25

    申请人： Yu-Lien Huang ,  Chun Hsiung Tsai ,  Chii-Ming Wu ,  Ziwei Fang

    发明人： Yu-Lien Huang ,  Chun Hsiung Tsai ,  Chii-Ming Wu ,  Ziwei Fang

    IPC分类号： H01L29/76

    CPC分类号： H01L21/76237 ,  H01L21/02321 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/76224

    摘要： The embodiments described provide methods and structures for doping oxide in the STIs with carbon to make etch rate in the narrow and wide structures equal and also to make corners of wide STIs strong. Such carbon doping can be performed by ion beam (ion implant) or by plasma doping. The hard mask layer can be used to protect the silicon underneath from doping. By using the doping mechanism, the even surface topography of silicon and STI enables patterning of gate structures and ILD0 gapfill for advanced processing technology.

    摘要翻译： 所描述的实施例提供了用碳掺杂氧化物的方法和结构，以使窄和宽结构中的蚀刻速率相等并且也使得宽STI的拐角变强。 这种碳掺杂可以通过离子束（离子注入）或通过等离子体掺杂来进行。 硬掩模层可用于保护下面的硅不被掺杂。 通过使用掺杂机制，硅和STI的均匀表面形貌使得门结构和ILD0间隙填充的图案化能够用于先进的加工技术。

    MECHANISMS FOR FORMING ULTRA SHALLOW JUNCTION
    4.
    发明申请
    MECHANISMS FOR FORMING ULTRA SHALLOW JUNCTION 有权
    形成超声结构的机制

    公开(公告)号：US20120112248A1

    公开(公告)日：2012-05-10

    申请号：US12941509

    申请日：2010-11-08

    申请人： Chii-Ming Wu ,  Yu Lien Huang ,  Chun Hsiung Tsai

    发明人： Chii-Ming Wu ,  Yu Lien Huang ,  Chun Hsiung Tsai

    IPC分类号： H01L29/78 ,  H01L21/265

    CPC分类号： H01L29/7831 ,  H01L21/2236 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/66803

    摘要： The embodiments of methods and structures are for doping fin structures by plasma doping processes to enable formation of shallow lightly doped source and drain (LDD) regions. The methods involve a two-step plasma doping process. The first step plasma process uses a heavy carrier gas, such as a carrier gas with an atomic weight equal to or greater than about 20 amu, to make the surfaces of fin structures amorphous and to reduce the dependence of doping rate on crystalline orientation. The second step plasma process uses a lighter carrier gas, which is lighter than the carrier gas for the first step plasma process, to drive the dopants deeper into the fin structures. The two-step plasma doping process produces uniform dopant profile beneath the outer surfaces of the fin structures.

    摘要翻译： 方法和结构的实施例用于通过等离子体掺杂工艺掺杂鳍结构，以形成浅掺杂的源极和漏极（LDD）区域。 该方法涉及两步等离子体掺杂工艺。 第一级等离子体工艺使用重载气，例如原子量等于或大于约20amu的载气，以使翅片结构的表面无定形并且降低掺杂速率对晶体取向的依赖性。 第二级等离子体处理使用比用于第一级等离子体处理的载气轻的载气，以将掺杂剂更深地驱动到鳍结构中。 两级等离子体掺杂工艺在翅片结构的外表面下方产生均匀的掺杂剂分布。

    Mechanisms for forming ultra shallow junction
    5.
    发明授权
    Mechanisms for forming ultra shallow junction 有权
    形成超浅结的机理

    公开(公告)号：US08298925B2

    公开(公告)日：2012-10-30

    申请号：US12941509

    申请日：2010-11-08

    申请人： Chii-Ming Wu ,  Yu Lien Huang ,  Chun Hsiung Tsai

    发明人： Chii-Ming Wu ,  Yu Lien Huang ,  Chun Hsiung Tsai

    IPC分类号： H01L21/26 ,  H01L21/425 ,  H01L21/02

    CPC分类号： H01L29/7831 ,  H01L21/2236 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/66803

    摘要： The embodiments of methods and structures are for doping fin structures by plasma doping processes to enable formation of shallow lightly doped source and drain (LDD) regions. The methods involve a two-step plasma doping process. The first step plasma process uses a heavy carrier gas, such as a carrier gas with an atomic weight equal to or greater than about 20 amu, to make the surfaces of fin structures amorphous and to reduce the dependence of doping rate on crystalline orientation. The second step plasma process uses a lighter carrier gas, which is lighter than the carrier gas for the first step plasma process, to drive the dopants deeper into the fin structures. The two-step plasma doping process produces uniform dopant profile beneath the outer surfaces of the fin structures.

    摘要翻译： 方法和结构的实施例用于通过等离子体掺杂工艺掺杂鳍结构，以形成浅掺杂的源极和漏极（LDD）区域。 该方法涉及两步等离子体掺杂工艺。 第一级等离子体工艺使用重载气，例如原子量等于或大于约20amu的载气，以使翅片结构的表面无定形并且降低掺杂速率对晶体取向的依赖性。 第二级等离子体处理使用比用于第一级等离子体处理的载气轻的载气，以将掺杂剂更深地驱动到鳍结构中。 两级等离子体掺杂工艺在翅片结构的外表面下方产生均匀的掺杂剂分布。

    Rapid thermal annealing to reduce pattern effect
    7.
    发明授权
    Rapid thermal annealing to reduce pattern effect 有权
    快速热退火降低图案效果

    公开(公告)号：US08753980B2

    公开(公告)日：2014-06-17

    申请号：US13753928

    申请日：2013-01-30

    申请人： Chun Hsiung Tsai ,  Chii-Ming Wu ,  Da-Wen Lin

    发明人： Chun Hsiung Tsai ,  Chii-Ming Wu ,  Da-Wen Lin

    IPC分类号： H01L21/44

    CPC分类号： H01L21/324 ,  H01L21/26513 ,  H01L21/67248

    摘要： A method of performing rapid thermal annealing on a substrate including heating the substrate to a first temperature in a rapid thermal annealing system having a front-side heating source and a backside heating source. The method further includes raising the temperature of the substrate from the first temperature to a second temperature greater than the first temperature. The backside heating source provides a greater amount of heat than the front-side heating source during the raising of the temperature of the substrate.

    摘要翻译： 在基板上进行快速热退火的方法，包括在具有前侧加热源和背面加热源的快速热退火系统中将基板加热到第一温度。 该方法还包括将衬底的温度从第一温度升高到大于第一温度的第二温度。 在提高衬底的温度期间，背面加热源提供比前侧加热源更大量的热量。

    Asymmetric rapid thermal annealing to reduce pattern effect
    9.
    发明授权
    Asymmetric rapid thermal annealing to reduce pattern effect 有权
    不对称快速热退火降低图案效果

    公开(公告)号：US08383513B2

    公开(公告)日：2013-02-26

    申请号：US12898037

    申请日：2010-10-05

    申请人： Chun Hsiung Tsai ,  Chii-Ming Wu ,  Da-Wen Lin

    发明人： Chun Hsiung Tsai ,  Chii-Ming Wu ,  Da-Wen Lin

    IPC分类号： H01L21/44 ,  H01L21/8238

    CPC分类号： H01L21/324 ,  H01L21/26513 ,  H01L21/67248

    摘要： Rapid thermal annealing methods and systems for annealing patterned substrates with minimal pattern effect on substrate temperature non-uniformity are provided. The rapid thermal annealing system includes a front-side heating source and a backside heating source. The backside heating source of the rapid thermal annealing system supplies a dominant amount of heat to bring the substrate temperature to the peak annealing temperature. The front-side heating source contributes to heat up the environment near the front-side of the substrate to a temperature lower than about 100° C. to about 200° C. less than the peak annealing temperature. The asymmetric front-side and backside heating for rapid thermal annealing reduce or eliminate pattern effect and improve WIW and WID device performance uniformity.

    摘要翻译： 提供了用于退火图案化衬底的快速热退火方法和系统，对衬底温度的不均匀性具有最小的图案效应。 快速热退火系统包括前侧加热源和背面加热源。 快速热退火系统的背面加热源提供显着的热量以使衬底温度达到峰值退火温度。 前侧加热源有助于将基板前侧附近的环境加热至比峰退火温度低约100℃至约200℃的温度。 用于快速热退火的不对称前侧和后侧加热减少或消除图案效应，并提高WIW和WID器件的性能均匀性。