公开(公告)号：US10128115B2

公开(公告)日：2018-11-13

申请号：US12713356

申请日：2010-02-26

申请人： Chun-Feng Nieh ,  Mao-Rong Yeh ,  Chun Hsiung Tsai ,  Chii-Ming Wu

发明人： Chun-Feng Nieh ,  Mao-Rong Yeh ,  Chun Hsiung Tsai ,  Chii-Ming Wu

IPC分类号： H01L21/00 ,  H01L21/265 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/10

摘要： A method of forming MOS transistor includes the steps of performing a pocket implantation process on a substrate having a gate stack, performing a co-implanted ion implantation process on the substrate at a temperature less than room temperature, performing a lightly doped source/drain implantation process on the substrate, and forming source and drain regions in the substrate, adjacent the gate stack.

公开(公告)号：US20110212590A1

公开(公告)日：2011-09-01

申请号：US12713735

申请日：2010-02-26

申请人： Chii-Ming Wu ,  Chun-Feng Nieh

发明人： Chii-Ming Wu ,  Chun-Feng Nieh

IPC分类号： H01L21/336 ,  H01L21/265

CPC分类号： H01L21/26506 ,  H01L21/2658 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7848

摘要： An integrated circuit device and method of fabricating the integrated circuit device is disclosed. According to one of the broader forms of the invention, a method involves providing a semiconductor substrate. A combination of a pre-amorphous implantation process, a high temperature carbon implantation process, and/or an annealing process are performed on the substrate to form a stressor region.

摘要翻译： 公开了一种集成电路器件及其制造方法。 根据本发明的更广泛形式之一，涉及提供半导体衬底的方法。 在基板上进行预非晶注入工艺，高温碳注入工艺和/或退火工艺的组合以形成应力区域。

公开(公告)号：US08569139B2

公开(公告)日：2013-10-29

申请号：US12913041

申请日：2010-10-27

申请人： Chun-Feng Nieh ,  Ming-Huan Tsai ,  Wei-Han Fan ,  Yimin Huang ,  Chun-Fai Cheng ,  Han-Ting Tsai ,  Chii-Ming Wu

发明人： Chun-Feng Nieh ,  Ming-Huan Tsai ,  Wei-Han Fan ,  Yimin Huang ,  Chun-Fai Cheng ,  Han-Ting Tsai ,  Chii-Ming Wu

IPC分类号： H01L21/336 ,  H01L21/461

CPC分类号： H01L21/823814 ,  H01L21/26586 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of an integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite to the LDD region.

公开(公告)号：US07994016B2

公开(公告)日：2011-08-09

申请号：US12616406

申请日：2009-11-11

申请人： Chun-Hsiung Tsai ,  Chun-Feng Nieh ,  Da-Wen Lin ,  Chien-Tai Chan

发明人： Chun-Hsiung Tsai ,  Chun-Feng Nieh ,  Da-Wen Lin ,  Chien-Tai Chan

IPC分类号： H01L21/336

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of forming ultra-shallow p-type lightly doped drain (LDD) regions of a PMOS transistor in a surface of a substrate includes the steps of providing a gaseous mixture of an inert gas, a boron-containing source, and an optional carbon-containing source, wherein the concentration of the gaseous mixture is at least 99.5% dilute with the inert gas and the optional carbon-containing source, if present, forming the gaseous mixture into a plasma, and forming the LDD regions, wherein the forming step includes plasma-doping the boron into the substrate using the plasma. N-type pocket regions are formed in the substrate underneath and adjacent to the LDD regions, wherein for a PMOS transistor having a threshold voltage of 100 mV, the n-type pocket regions include phosphorous impurities at a dopant concentration of less than 6.0×1018 atoms/cm3 or a proportionately lower/higher dopant concentration for a lower/higher threshold voltage.

摘要翻译： 在衬底的表面中形成PMOS晶体管的超浅p型轻掺杂漏极（LDD）区域的方法包括以下步骤：提供惰性气体，含硼源和任选的碳的气态混合物 其中气态混合物的浓度与惰性气体和任选的含碳源（如果存在）一起稀释至少99.5％，将气态混合物形成等离子体，并形成LDD区域，其中形成步骤 包括使用等离子体将硼等离子体掺杂到衬底中。 在LDD区域下方并与LDD区域相邻的衬底中形成N型口袋区域，其中对于阈值电压为100mV的PMOS晶体管，n型袋区域包括掺杂剂浓度小于6.0×1018的磷杂质 原子/ cm 3或低/高阈值电压的比例较低/较高掺杂剂浓度。

公开(公告)号：US20110039390A1

公开(公告)日：2011-02-17

申请号：US12784348

申请日：2010-05-20

申请人： Chun-Feng Nieh ,  Chun Hsiung Tsai ,  Yuan-Hung Chiu ,  Hun-Jan Tao

发明人： Chun-Feng Nieh ,  Chun Hsiung Tsai ,  Yuan-Hung Chiu ,  Hun-Jan Tao

IPC分类号： H01L21/336

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/26593 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of forming an integrated circuit includes providing a semiconductor wafer, and forming a metal-oxide-semiconductor (MOS) device. The step of forming the MOS device includes forming a gate stack on the semiconductor wafer, and performing a cryo-implantation to form an implantation region adjacent the gate stack at a wafer temperature lower than 0° C. The step of performing the cryo-implantation is selected from the group consisting essentially of implanting the semiconductor wafer to form a pre-amorphized implantation (PAI) region; implanting the semiconductor wafer to form a lightly-doped source/drain region; implanting the semiconductor wafer to form a pocket/halo region; implanting the semiconductor wafer to form a deep source/drain region, and combinations thereof

摘要翻译： 形成集成电路的方法包括提供半导体晶片和形成金属氧化物半导体（MOS）器件。 形成MOS器件的步骤包括在半导体晶片上形成栅极堆叠，并且在低于0℃的晶片温度下进行低温注入以形成与栅叠层相邻的注入区。进行低温注入 选自基本上由植入半导体晶片以形成预非晶化植入（PAI）区域的组; 注入半导体晶片以形成轻掺杂的源/漏区; 注入半导体晶片以形成口/晕区域; 注入半导体晶片以形成深源极/漏极区及其组合

公开(公告)号：US20140015104A1

公开(公告)日：2014-01-16

申请号：US13548783

申请日：2012-07-13

申请人： Yu-Chen Su ,  Huang-Ming Chen ,  Chun-Feng Nieh ,  Pei-Chao Su

发明人： Yu-Chen Su ,  Huang-Ming Chen ,  Chun-Feng Nieh ,  Pei-Chao Su

IPC分类号： H01L21/38 ,  H01L29/772

CPC分类号： H01L29/0638 ,  H01L21/225 ,  H01L21/26586 ,  H01L21/31155 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76834 ,  H01L21/76897 ,  H01L27/092 ,  H01L29/165 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

摘要： An embodiment is a method comprising diffusing carbon through a surface of a substrate, implanting carbon through the surface of the substrate, and annealing the substrate after the diffusing the carbon and implanting the carbon through the surface of the substrate. The substrate comprises a first gate, a gate spacer, an etch stop layer, and an inter-layer dielectric. The first gate is over a semiconductor substrate. The gate spacer is along a sidewall of the first gate. The etch stop layer is on a surface of the gate spacer and over a surface of the semiconductor substrate. The inter-layer dielectric is over the etch stop layer. The surface of the substrate comprises a surface of the inter-layer dielectric.

摘要翻译： 一个实施方案是一种方法，其包括通过基底的表面扩散碳，通过基底的表面注入碳，以及在扩散碳并将碳注入到基底的表面之后退火基底。 衬底包括第一栅极，栅极间隔物，蚀刻停止层和层间电介质。 第一个栅极在半导体衬底之上。 栅极间隔物沿着第一栅极的侧壁。 蚀刻停止层位于栅极间隔物的表面上并在半导体衬底的表面上方。 层间电介质在蚀刻停止层之上。 衬底的表面包括层间电介质的表面。

公开(公告)号：US08629013B2

公开(公告)日：2014-01-14

申请号：US13273463

申请日：2011-10-14

申请人： Chun-Feng Nieh ,  Chung-Yi Yu ,  Hung-Ta Lin

发明人： Chun-Feng Nieh ,  Chung-Yi Yu ,  Hung-Ta Lin

IPC分类号： H01L21/338

CPC分类号： H01L29/66522 ,  H01L21/2654 ,  H01L29/267

摘要： Provided is a method of fabricating a semiconductor device. The method includes forming a first III-V family layer over a substrate. The first III-V family layer includes a surface having a first surface morphology. The method includes performing an ion implantation process to the first III-V family layer through the surface. The ion implantation process changes the first surface morphology into a second surface morphology. After the ion implantation process is performed, the method includes forming a second III-V family layer over the first III-V family layer. The second III-V family layer has a material composition different from that of the first III-V family layer.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括在衬底上形成第一III-V族层。 第一III-V族层包括具有第一表面形态的表面。 该方法包括通过表面对第一III-V族层执行离子注入工艺。 离子注入工艺将第一表面形态变为第二表面形态。 在执行离子注入工艺之后，该方法包括在第一III-V族层上形成第二III-V族层。 第二III-V族层具有不同于第一III-V族层的材料组成。

公开(公告)号：US07741699B2

公开(公告)日：2010-06-22

申请号：US11521660

申请日：2006-09-15

申请人： Keh-Chiang Ku ,  Chun-Feng Nieh ,  Li-Ping Huang ,  Chih-Chiang Wang ,  Chien-Hao Chen ,  Hsun Chang ,  Li-Ting Wang ,  Tze-Liang Lee ,  Shih-Chang Chen

发明人： Keh-Chiang Ku ,  Chun-Feng Nieh ,  Li-Ping Huang ,  Chih-Chiang Wang ,  Chien-Hao Chen ,  Hsun Chang ,  Li-Ting Wang ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC分类号： H01L29/00

CPC分类号： H01L21/26586 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device includes a gate stack over a semiconductor substrate, a lightly doped n-type source/drain (LDD) region in the semiconductor substrate and adjacent the gate stack wherein the LDD region comprises an n-type impurity, a heavily doped n-type source/drain (N+ S/D) region in the semiconductor substrate and adjacent the gate stack wherein the N+ S/D region comprises an n-type impurity, a pre-amorphized implantation (PAI) region in the semiconductor substrate wherein the PAI region comprises an end of range (EOR) region, and an interstitial blocker region in the semiconductor substrate wherein the interstitial blocker region has a depth greater than a depth of the LDD region but less than a depth of the EOR region.

摘要翻译： 半导体器件包括在半导体衬底上的栅极堆叠，半导体衬底中的轻掺杂n型源极/漏极（LDD）区域并且邻近栅极堆叠，其中LDD区域包括n型杂质，重掺杂n- （N + S / D）区，其中N + S / D区包括n型杂质，半导体衬底中的非淀粉化注入（PAI）区，其中PAI 区域包括端部范围（EOR）区域和半导体衬底中的间隙阻挡区域，其中间隙阻挡区域的深度大于LDD区域的深度但小于EOR区域的深度。

公开(公告)号：US20130078783A1

公开(公告)日：2013-03-28

申请号：US13244340

申请日：2011-09-24

申请人： Chun-Feng Nieh ,  Chung-Yi Yu ,  Hung-Ta Lin

发明人： Chun-Feng Nieh ,  Chung-Yi Yu ,  Hung-Ta Lin

IPC分类号： H01L21/762

CPC分类号： H01L21/76224

摘要： Provided is a method of fabricating a semiconductor device. The method includes forming a first dielectric layer over a first surface and a second surface of a silicon substrate. the first and second surfaces being opposite surfaces. A first portion of the first dielectric layer covers the first surface of the substrate, and a second portion of the first dielectric layer covers the second surface of the substrate. The method includes forming openings that extend into the substrate from the first surface. The method includes filling the openings with a second dielectric layer. The method includes removing the first portion of the first dielectric layer without removing the second portion of the first dielectric layer.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括在硅衬底的第一表面和第二表面上形成第一电介质层。 第一和第二表面是相对的表面。 第一介电层的第一部分覆盖基板的第一表面，并且第一介电层的第二部分覆盖基板的第二表面。 该方法包括形成从第一表面延伸到基底中的开口。 该方法包括用第二介电层填充开口。 该方法包括在不去除第一介电层的第二部分的情况下去除第一介电层的第一部分。

公开(公告)号：US08273633B2

公开(公告)日：2012-09-25

申请号：US11690869

申请日：2007-03-26

申请人： Keh-Chiang Kuo ,  Chien-Hao Chen ,  Chun-Feng Nieh ,  Li-Ping Huang ,  Hsun Chang ,  Li-Ting Wang ,  Chih-Chiang Wang ,  Tze-Liang Lee

发明人： Keh-Chiang Kuo ,  Chien-Hao Chen ,  Chun-Feng Nieh ,  Li-Ping Huang ,  Hsun Chang ,  Li-Ting Wang ,  Chih-Chiang Wang ,  Tze-Liang Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/2686 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/823878

摘要： A method of enhancing dopant activation without suffering additional dopant diffusion, includes forming shallow and lightly-doped source/drain extension regions in a semiconductor substrate, performing a first anneal process on the source/drain extension regions, forming deep and heavily-doped source/drain regions in the substrate adjacent to the source/drain extension regions, and performing a second anneal process on source/drain regions. The first anneal process is a flash anneal process performed for a time of between about 1 millisecond and 3 milliseconds, and the second anneal process is a rapid thermal anneal process performed for a time of between about 1 second and 30 seconds.

摘要翻译： 增加掺杂剂激活而不会受到额外的掺杂剂扩散的方法包括在半导体衬底中形成浅掺杂的和轻掺杂的源极/漏极扩展区，在源极/漏极延伸区上执行第一退火工艺，形成深和重掺杂的源/ 漏极区域，并且在源极/漏极区域上执行第二退火处理。 第一退火工艺是在约1毫秒至3毫秒之间的时间内执行的闪光退火工艺，第二退火工艺是在约1秒至30秒之间进行的快速热退火工艺。