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1.发明申请Forming Seed Layer in Nano-Trench Structure Using Net Deposition and Net Etch 审中-公开使用净沉积和净蚀刻在纳米沟槽结构中形成种子层公开(公告)号：US20090127097A1
公开(公告)日：2009-05-21
申请号：US11941435
申请日：2007-11-16
申请人： Kei-Wei Chen , Shih-Ho Lin , Yu-Sheng Wang , Szu-An Wu , Ying-Lang Wang
发明人： Kei-Wei Chen , Shih-Ho Lin , Yu-Sheng Wang , Szu-An Wu , Ying-Lang Wang
IPC分类号： C23C14/00
CPC分类号： C23C14/345 , C23C14/046 , H01L21/76862 , H01L21/76873
摘要： A method of forming an integrated circuit structure includes forming a dielectric layer; forming an opening in the dielectric layer; performing a net deposition step to form a seed layer having a portion in the opening, wherein the net deposition step comprises a first deposition and a first etching; performing a net etch step to the seed layer, wherein the net etch step comprises a first etching and a first deposition, wherein a portion of the seed layer remains after the net etch step; and growing a conductive material on the seed layer to fill a remaining portion of the opening.
摘要翻译： 形成集成电路结构的方法包括形成电介质层; 在介电层中形成开口; 执行净沉积步骤以形成具有在开口中的一部分的种子层，其中所述净沉积步骤包括第一沉积和第一蚀刻; 对所述种子层进行净蚀刻步骤，其中所述净蚀刻步骤包括第一蚀刻和第一沉积，其中所述种子层的一部分在所述净蚀刻步骤之后保留; 以及在种子层上生长导电材料以填充开口的剩余部分。
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公开(公告)号：US08470390B2
公开(公告)日：2013-06-25
申请号：US11972785
申请日：2008-01-11
申请人： Yu-Sheng Wang , Shih-Ho Lin , Kei-Wei Chen , Szu-An Wu , Ying-Lang Wang
发明人： Yu-Sheng Wang , Shih-Ho Lin , Kei-Wei Chen , Szu-An Wu , Ying-Lang Wang
CPC分类号： H01L21/76814 , H01L21/02063 , H01L21/76828 , H01L21/76843
摘要： A method of forming an integrated circuit structure includes providing a substrate; forming a metal feature over the substrate; forming a dielectric layer over the metal feature; and forming an opening in the dielectric layer. At least a portion of the metal feature is exposed through the opening. An oxide layer is accordingly formed on an exposed portion of the metal feature. The method further includes, in a production tool having a vacuum environment, performing an oxide-removal process to remove the oxide layer. Between the step of forming the opening and the oxide-removal process, no additional oxide-removal process is performed to the metal feature outside the production tool. The method further includes, in the production tool, forming a diffusion barrier layer in the opening, and forming a seed layer on the diffusion barrier layer.
摘要翻译： 形成集成电路结构的方法包括提供基板; 在衬底上形成金属特征; 在金属特征上形成介电层; 并在介电层中形成开口。 金属特征的至少一部分通过开口露出。 相应地，在金属特征的暴露部分上形成氧化物层。 该方法还包括在具有真空环境的生产工具中进行氧化物去除工艺以去除氧化物层。 在形成开口的步骤和氧化物去除工艺之间，对生产工具外部的金属特征没有进行额外的氧化物去除处理。 该方法还包括在生产工具中在开口中形成扩散阻挡层，并在扩散阻挡层上形成种子层。
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公开(公告)号：US20090181164A1
公开(公告)日：2009-07-16
申请号：US11972785
申请日：2008-01-11
申请人： Yu-Sheng Wang , Shih-Ho Lin , Kei-Wei Chen , Szu-An Wu , Ying-Lang Wang
发明人： Yu-Sheng Wang , Shih-Ho Lin , Kei-Wei Chen , Szu-An Wu , Ying-Lang Wang
IPC分类号： H05K3/46
CPC分类号： H01L21/76814 , H01L21/02063 , H01L21/76828 , H01L21/76843
摘要： A method of forming an integrated circuit structure includes providing a substrate; forming a metal feature over the substrate; forming a dielectric layer over the metal feature; and forming an opening in the dielectric layer. At least a portion of the metal feature is exposed through the opening. An oxide layer is accordingly formed on an exposed portion of the metal feature. The method further includes, in a production tool having a vacuum environment, performing an oxide-removal process to remove the oxide layer. Between the step of forming the opening and the oxide-removal process, no additional oxide-removal process is performed to the metal feature outside the production tool. The method further includes, in the production tool, forming a diffusion barrier layer in the opening, and forming a seed layer on the diffusion barrier layer
摘要翻译： 形成集成电路结构的方法包括提供基板; 在衬底上形成金属特征; 在金属特征上形成介电层; 并在介电层中形成开口。 金属特征的至少一部分通过开口露出。 相应地，在金属特征的暴露部分上形成氧化物层。 该方法还包括在具有真空环境的生产工具中进行氧化物去除工艺以去除氧化物层。 在形成开口的步骤和氧化物去除工艺之间，对生产工具外部的金属特征没有进行额外的氧化物去除处理。 该方法还包括在生产工具中在开口中形成扩散阻挡层，并在扩散阻挡层上形成种子层
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公开(公告)号：US08247322B2
公开(公告)日：2012-08-21
申请号：US11680981
申请日：2007-03-01
IPC分类号： H01L21/44
CPC分类号： H01L21/76831 , H01L21/7684
摘要： A method for forming a semiconductor structure includes forming a dielectric layer over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is then formed and a single polishing operation removes the seed layer and conductive layer.
摘要翻译： 形成半导体结构的方法包括在衬底上形成电介质层。 在电介质层上形成第一非导电阻挡层。 通过第一非导电阻挡层和介电层内形成至少一个开口。 在第一非导电阻挡层上并在开口内形成第二非导电阻挡层。 去除第二非导电阻挡层的至少一部分，从而至少部分地暴露第一非导电阻挡层的顶表面和开口的底表面，而第二非导电阻挡层保留在侧壁上 的开幕。 然后形成种子层和导电层，并且单次抛光操作去除种子层和导电层。
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公开(公告)号：US08552529B2
公开(公告)日：2013-10-08
申请号：US13488958
申请日：2012-06-05
申请人： Jung-Chih Tsao , Yu-Sheng Wang , Kei-Wei Chen , Ying-Lang Wang
发明人： Jung-Chih Tsao , Yu-Sheng Wang , Kei-Wei Chen , Ying-Lang Wang
IPC分类号： H01L21/02
CPC分类号： H01L27/0805 , H01L28/60 , H01L28/75
摘要： A semiconductor device is disclosed. The device includes a substrate; a first metal layer overlying the substrate; a dielectric layer overlying the first metal layer; and a second metal layer overlying the dielectric layer, wherein the first metal layer comprises: a first body-centered cubic lattice metal layer; a first underlayer, underlying the first body-centered cubic lattice metal layer, wherein the first underlayer is metal of body-centered cubic lattice and includes titanium (Ti), tungsten (W), molybdenum (Mo) or niobium (Nb); and a first interface of body-centered cubic lattice between the first body-centered cubic lattice metal layer and the first underlayer.
摘要翻译： 公开了一种半导体器件。 该装置包括基板; 覆盖衬底的第一金属层; 覆盖在第一金属层上的电介质层; 以及覆盖所述电介质层的第二金属层，其中所述第一金属层包括：第一体心立方晶格金属层; 第一底层，位于第一体心立方晶格金属层下面，其中第一底层是体心立方晶格的金属，包括钛（Ti），钨（W），钼（Mo）或铌（Nb）; 以及在第一体心立方晶格金属层和第一底层之间的体心立方晶格的第一界面。
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公开(公告)号：US20080211106A1
公开(公告)日：2008-09-04
申请号：US11680981
申请日：2007-03-01
IPC分类号： H01L21/4763
CPC分类号： H01L21/76831 , H01L21/7684
摘要： A method for forming a semiconductor structure includes forming a dielectric layer over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is then formed and a single polishing operation removes the seed layer and conductive layer.
摘要翻译： 形成半导体结构的方法包括在衬底上形成电介质层。 在电介质层上形成第一非导电阻挡层。 通过第一非导电阻挡层和介电层内形成至少一个开口。 在第一非导电阻挡层上并在开口内形成第二非导电阻挡层。 去除第二非导电阻挡层的至少一部分，从而至少部分地暴露第一非导电阻挡层的顶表面和开口的底表面，而第二非导电阻挡层保留在侧壁上 的开幕。 然后形成种子层和导电层，并且单次抛光操作去除种子层和导电层。
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公开(公告)号：US08531036B2
公开(公告)日：2013-09-10
申请号：US13563495
申请日：2012-07-31
IPC分类号： H01L23/48
CPC分类号： H01L21/76831 , H01L21/7684
摘要： A semiconductor structure is provided and includes a dielectric layer disposed over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is disposed in the opening.
摘要翻译： 提供半导体结构，并且包括设置在基板上的电介质层。 在电介质层上形成第一非导电阻挡层。 通过第一非导电阻挡层和介电层内形成至少一个开口。 在第一非导电阻挡层上并在开口内形成第二非导电阻挡层。 去除第二非导电阻挡层的至少一部分，从而至少部分地暴露第一非导电阻挡层的顶表面和开口的底表面，而第二非导电阻挡层保留在侧壁上 的开幕。 种子层和导电层设置在开口中。
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公开(公告)号：US20120292768A1
公开(公告)日：2012-11-22
申请号：US13563495
申请日：2012-07-31
IPC分类号： H01L23/52
CPC分类号： H01L21/76831 , H01L21/7684
摘要： A semiconductor structure is provided and includes a dielectric layer disposed over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is disposed in the opening.
摘要翻译： 提供半导体结构，并且包括设置在基板上的电介质层。 在电介质层上形成第一非导电阻挡层。 通过第一非导电阻挡层和介电层内形成至少一个开口。 在第一非导电阻挡层上并在开口内形成第二非导电阻挡层。 去除第二非导电阻挡层的至少一部分，从而至少部分地暴露第一非导电阻挡层的顶表面和开口的底表面，而第二非导电阻挡层保留在侧壁上 的开幕。 种子层和导电层设置在开口中。
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公开(公告)号：US20080251889A1
公开(公告)日：2008-10-16
申请号：US11733897
申请日：2007-04-11
申请人： Jung-Chih Tsao , Yu-Sheng Wang , Kei-Wei Chen , Ying-Lang Wang
发明人： Jung-Chih Tsao , Yu-Sheng Wang , Kei-Wei Chen , Ying-Lang Wang
IPC分类号： H01L29/00
CPC分类号： H01L27/0805 , H01L28/60 , H01L28/75
摘要： A semiconductor device is disclosed. The device includes a substrate, a first metal layer, a dielectric layer, and a second metal layer. The first metal layer comprises a body-centered cubic lattice metal, and overlies the substrate. The dielectric layer overlies the first metal layer. The second metal layer overlies the dielectric layer.
摘要翻译： 公开了一种半导体器件。 该器件包括衬底，第一金属层，电介质层和第二金属层。 第一金属层包括体心立方晶格金属，并且覆盖在基底上。 电介质层覆盖在第一金属层上。 第二金属层覆盖在电介质层上。
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公开(公告)号：US20070257366A1
公开(公告)日：2007-11-08
申请号：US11416945
申请日：2006-05-03
IPC分类号： H01L21/4763
CPC分类号： H01L21/76846 , H01L21/76844 , H01L21/76865
摘要： A method for producing a semiconductor-device having an electrical interconnect. The method produces having an improved barrier layer between the interconnect conductor and the dielectric material in which the interconnect recess is formed. A dielectric layer is formed on top of a wafer substrate having at least one contact region. An interconnect for servicing the contact region is fabricated by forming an interconnect recess and then depositing a primary barrier layer of tantalum nitride and subjecting it to a re-sputtering operation. A film layer of tantalum is then deposited and re-sputtered. Following this operation, a seed layer is formed, and then a conductor is used to fill the interconnect recess. Planerizing the surface of the wafer so that further fabrication may be performed may complete the process.
摘要翻译： 一种具有电互连的半导体器件的制造方法。 该方法产生在互连导体和形成有互连凹槽的电介质材料之间具有改进的阻挡层。 在具有至少一个接触区域的晶片衬底的顶部上形成电介质层。 通过形成互连凹槽然后沉积氮化钽的主阻挡层并对其进行再溅射操作来制造用于维护接触区域的互连。 然后沉积钽薄膜层并重新溅射。 在该操作之后，形成种子层，然后使用导体来填充互连凹槽。 使晶片的表面平整化，以便进一步制造可以完成该工艺。
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